From dd27a60daa00b0fd930f14e9a144a2a0a5758ebc Mon Sep 17 00:00:00 2001 From: "Wesley W. Terpstra" Date: Tue, 30 Aug 2016 10:40:54 -0700 Subject: [PATCH] tilelink2: use consistent in/out ports for TLSimpleFactories --- uncore/src/main/scala/tilelink2/RegisterRouter.scala | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/uncore/src/main/scala/tilelink2/RegisterRouter.scala b/uncore/src/main/scala/tilelink2/RegisterRouter.scala index 35ff80d5..890e4a0b 100644 --- a/uncore/src/main/scala/tilelink2/RegisterRouter.scala +++ b/uncore/src/main/scala/tilelink2/RegisterRouter.scala @@ -64,7 +64,7 @@ abstract class TLRegFactory(address: AddressSet, concurrency: Option[Int], beatB val node = TLRegisterNode(address, concurrency, beatBytes) } -class TLRegBundle[P](val params: P, val tl_in: Vec[TLBundle]) extends Bundle +class TLRegBundle[P](val params: P, val in: Vec[TLBundle]) extends Bundle class TLRegModule[P, B <: Bundle](val params: P, bundleBuilder: => B, factory: TLRegFactory) extends TLModule(factory) with HasRegMap