riscv/rocket-chip
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generate BootROM contents from assembly code

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This commit is contained in:
Howard Mao 2016-08-05 11:07:42 -07:00
parent dab96096b4
commit dd1fed41b6
11 changed files with 49 additions and 19 deletions
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2
Makefrag
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@ -39,6 +39,8 @@ endif
timeout_cycles = 100000000
bootrom_img = $(base_dir)/bootrom/bootrom.img
#--------------------------------------------------------------------
# DRAMSim2
#--------------------------------------------------------------------

1
bootrom/.gitignore vendored Normal file
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@ -0,0 +1 @@
*.elf

12
bootrom/Makefile Normal file
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@ -0,0 +1,12 @@
bootrom_img = bootrom.img
GCC=riscv64-unknown-elf-gcc
OBJCOPY=riscv64-unknown-elf-objcopy
all: $(bootrom_img)
%.img: %.elf
$(OBJCOPY) -O binary --change-addresses=-0x1000 --only-section .text $< $@
%.elf: %.S linker.ld
$(GCC) -Tlinker.ld $< -nostdlib -static -o $@

13
bootrom/bootrom.S Normal file
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@ -0,0 +1,13 @@
.text
.global _start
_start:
// This boot ROM doesn't know about any boot devices, so it just spins,
// waiting for the debugger to load a program and change the PC.
j _start // reset vector
.word 0 // reserved
.word 0 // reserved
.word 0 // pointer to config string
.word 0 // default trap vector
.word 0
.word 0
.word 0

BIN
bootrom/bootrom.img Executable file
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Binary file not shown.

5
bootrom/linker.ld Normal file
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@ -0,0 +1,5 @@
SECTIONS
{
. = 0x1000;
.text : { *(.text) }
}

4
emulator/Makefrag-verilator
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@ -9,12 +9,12 @@ verilog_debug = $(generated_dir_debug)/$(MODEL).$(CONFIG).v
.SECONDARY: $(firrtl) $(firrtl_debug) $(verilog) $(verilog_debug)
$(generated_dir)/%.$(CONFIG).fir $(generated_dir)/%.$(CONFIG).prm $(generated_dir)/%.$(CONFIG).d: $(chisel_srcs)
$(generated_dir)/%.$(CONFIG).fir $(generated_dir)/%.$(CONFIG).prm $(generated_dir)/%.$(CONFIG).d: $(chisel_srcs) $(bootrom_img)
mkdir -p $(dir $@)
cd $(base_dir) && $(SBT) "run $(PROJECT) $(MODEL) $(CONFIG) --targetDir $(generated_dir)"
mv $(generated_dir)/$(MODEL).fir $(generated_dir)/$(MODEL).$(CONFIG).fir
$(generated_dir_debug)/%.$(CONFIG).fir $(generated_dir_debug)/%.$(CONFIG).prm $(generated_dir_debug)/%.$(CONFIG).d: $(chisel_srcs)
$(generated_dir_debug)/%.$(CONFIG).fir $(generated_dir_debug)/%.$(CONFIG).prm $(generated_dir_debug)/%.$(CONFIG).d: $(chisel_srcs) $(bootrom_img)
mkdir -p $(dir $@)
cd $(base_dir) && $(SBT) "run $(PROJECT) $(MODEL) $(CONFIG) --targetDir $(generated_dir_debug)"
mv $(generated_dir_debug)/$(MODEL).fir $(generated_dir_debug)/$(MODEL).$(CONFIG).fir

1
src/main/scala/Configs.scala
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@ -315,6 +315,7 @@ class BaseConfig extends Config (
dataBeats = innerDataBeats,
dataBits = site(CacheBlockBytes) * 8)
}
case BootROMFile => "./bootrom/bootrom.img"
case TLKey("MMIO_Outermost") => site(TLKey("L2toMMIO")).copy(dataBeats = site(MIFDataBeats))
case NTiles => Knob("NTILES")
case AsyncMemChannels => false

23
src/main/scala/RocketChip.scala
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@ -13,6 +13,8 @@ import uncore.util._
import uncore.converters._
import rocket._
import rocket.Util._
import java.nio.{ByteBuffer,ByteOrder}
import java.nio.file.{Files, Paths}
/** Top-level parameters of RocketChip, values set in e.g. PublicConfigs.scala */
@ -56,6 +58,7 @@ case object PLICKey extends Field[PLICConfig]
/** Number of clock cycles per RTC tick */
case object RTCPeriod extends Field[Int]
case object AsyncDebugBus extends Field[Boolean]
case object BootROMFile extends Field[String]
/** Utility trait for quick access to some relevant parameters */
trait HasTopLevelParameters {
@ -271,25 +274,19 @@ class Uncore(implicit val p: Parameters) extends Module
}
def makeBootROM()(implicit p: Parameters) = {
val rom = java.nio.ByteBuffer.allocate(32)
rom.order(java.nio.ByteOrder.LITTLE_ENDIAN)
val romdata = Files.readAllBytes(Paths.get(p(BootROMFile)))
val rom = ByteBuffer.wrap(romdata)
rom.order(ByteOrder.LITTLE_ENDIAN)
// for now, have the reset vector jump straight to memory
val resetToMemDist = p(GlobalAddrMap)("mem").start - p(ResetVector)
require(resetToMemDist == (resetToMemDist.toInt >> 12 << 12))
val configStringAddr = p(ResetVector).toInt + rom.capacity
// This boot ROM doesn't know about any boot devices, so it just spins,
// waiting for the debugger to load a program and change the PC.
rom.putInt(0x0000006f) // loop forever
rom.putInt(0) // reserved
rom.putInt(0) // reserved
rom.putInt(configStringAddr) // pointer to config string
rom.putInt(0) // default trap vector
rom.putInt(0) // ...
rom.putInt(0) // ...
rom.putInt(0) // ...
require(rom.getInt(12) == 0,
"Config string address position should not be occupied by code")
rom.putInt(12, configStringAddr)
rom.array() ++ p(ConfigString).toSeq
}

5
src/main/scala/Testing.scala
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@ -4,7 +4,7 @@ package rocketchip
import Chisel._
import scala.collection.mutable.{LinkedHashSet,LinkedHashMap}
import cde.{Parameters, ParameterDump, Config, Field}
import cde.{Parameters, ParameterDump, Config, Field, CDEMatchError}
case object RegressionTestNames extends Field[LinkedHashSet[String]]
@ -203,8 +203,7 @@ object TestGenerator extends App {
}
currentConfig ++ finalConfig
}
val world = (new Config(finalConfig)).toInstance
val world = finalConfig.toInstance
val paramsFromConfig: Parameters = Parameters.root(world)

2
vsim/Makefrag-verilog
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@ -16,7 +16,7 @@ else
# files.
.SECONDARY: $(generated_dir)/$(MODEL).$(CONFIG).fir
$(generated_dir)/%.$(CONFIG).fir $(generated_dir)/%.$(CONFIG).d $(generated_dir)/%.prm: $(chisel_srcs)
$(generated_dir)/%.$(CONFIG).fir $(generated_dir)/%.$(CONFIG).d $(generated_dir)/%.prm: $(chisel_srcs) $(bootrom_img)
mkdir -p $(dir $@)
cd $(base_dir) && $(SBT) "run $(PROJECT) $(notdir $*) $(CONFIG) $(CHISEL_ARGS) --configDump --noInlineMem"
mv $(generated_dir)/$(MODEL).fir $(generated_dir)/$(MODEL).$(CONFIG).fir