462 lines
18 KiB
Scala
462 lines
18 KiB
Scala
// See LICENSE for license details.
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package rocketchip
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import Chisel._
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import cde.{Parameters, Field}
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import junctions._
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import uncore.tilelink._
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import uncore.coherence._
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import uncore.agents._
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import uncore.devices._
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import uncore.util._
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import uncore.converters._
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import rocket._
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import rocket.Util._
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import java.nio.{ByteBuffer,ByteOrder}
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import java.nio.file.{Files, Paths}
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/** Top-level parameters of RocketChip, values set in e.g. PublicConfigs.scala */
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/** Options for memory bus interface */
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object BusType {
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sealed trait EnumVal
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case object AXI extends EnumVal
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case object AHB extends EnumVal
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case object TL extends EnumVal
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val busTypes = Seq(AXI, AHB, TL)
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}
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/** Number of memory channels */
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case object AsyncMemChannels extends Field[Boolean]
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case object NMemoryChannels extends Field[Int]
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case object TMemoryChannels extends Field[BusType.EnumVal]
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/** Number of banks per memory channel */
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case object NBanksPerMemoryChannel extends Field[Int]
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/** Least significant bit of address used for bank partitioning */
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case object BankIdLSB extends Field[Int]
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/** Number of outstanding memory requests */
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case object NOutstandingMemReqsPerChannel extends Field[Int]
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/** Number of exteral MMIO ports */
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case object AsyncMMIOChannels extends Field[Boolean]
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case object ExtMMIOPorts extends Field[AddrMap]
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case object NExtMMIOAXIChannels extends Field[Int]
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case object NExtMMIOAHBChannels extends Field[Int]
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case object NExtMMIOTLChannels extends Field[Int]
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case object AsyncBusChannels extends Field[Boolean]
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case object NExtBusAXIChannels extends Field[Int]
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/** Function for building some kind of coherence manager agent */
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case object BuildL2CoherenceManager extends Field[(Int, Parameters) => CoherenceAgent]
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/** Function for building some kind of tile connected to a reset signal */
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case object BuildTiles extends Field[Seq[(Bool, Parameters) => Tile]]
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/** A string describing on-chip devices, readable by target software */
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case object ConfigString extends Field[Array[Byte]]
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/** Number of external interrupt sources */
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case object NExtInterrupts extends Field[Int]
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/** Interrupt controller configuration */
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case object PLICKey extends Field[PLICConfig]
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/** Number of clock cycles per RTC tick */
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case object RTCPeriod extends Field[Int]
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case object AsyncDebugBus extends Field[Boolean]
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case object BootROMFile extends Field[String]
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/** Utility trait for quick access to some relevant parameters */
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trait HasTopLevelParameters {
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implicit val p: Parameters
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lazy val nTiles = p(NTiles)
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lazy val nCachedTilePorts = p(NCachedTileLinkPorts)
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lazy val nUncachedTilePorts = p(NUncachedTileLinkPorts)
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lazy val csrAddrBits = 12
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lazy val tMemChannels = p(TMemoryChannels)
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lazy val nMemChannels = p(NMemoryChannels)
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lazy val nMemAXIChannels = if (tMemChannels == BusType.AXI) nMemChannels else 0
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lazy val nMemAHBChannels = if (tMemChannels == BusType.AHB) nMemChannels else 0
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lazy val nMemTLChannels = if (tMemChannels == BusType.TL) nMemChannels else 0
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lazy val nBanksPerMemChannel = p(NBanksPerMemoryChannel)
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lazy val nBanks = nMemChannels*nBanksPerMemChannel
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lazy val lsb = p(BankIdLSB)
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lazy val nMemReqs = p(NOutstandingMemReqsPerChannel)
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lazy val mifAddrBits = p(MIFAddrBits)
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lazy val mifDataBeats = p(MIFDataBeats)
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lazy val xLen = p(XLen)
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lazy val outermostParams = p.alterPartial({ case TLId => "Outermost" })
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lazy val outermostMMIOParams = p.alterPartial({ case TLId => "MMIO_Outermost" })
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}
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class MemBackupCtrlIO extends Bundle {
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val en = Bool(INPUT)
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val in_valid = Bool(INPUT)
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val out_ready = Bool(INPUT)
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val out_valid = Bool(OUTPUT)
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}
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/** Top-level io for the chip */
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class BasicTopIO(implicit val p: Parameters) extends ParameterizedBundle()(p)
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with HasTopLevelParameters
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class TopIO(implicit p: Parameters) extends BasicTopIO()(p) {
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val mem_clk = if (p(AsyncMemChannels)) Some(Vec(nMemChannels, Clock(INPUT))) else None
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val mem_rst = if (p(AsyncMemChannels)) Some(Vec(nMemChannels, Bool (INPUT))) else None
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val mem_axi = Vec(nMemAXIChannels, new NastiIO)
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val mem_ahb = Vec(nMemAHBChannels, new HastiMasterIO)
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val mem_tl = Vec(nMemTLChannels, new ClientUncachedTileLinkIO()(outermostParams))
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val interrupts = Vec(p(NExtInterrupts), Bool()).asInput
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val bus_clk = if (p(AsyncBusChannels)) Some(Vec(p(NExtBusAXIChannels), Clock(INPUT))) else None
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val bus_rst = if (p(AsyncBusChannels)) Some(Vec(p(NExtBusAXIChannels), Bool (INPUT))) else None
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val bus_axi = Vec(p(NExtBusAXIChannels), new NastiIO).flip
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val mmio_clk = if (p(AsyncMMIOChannels)) Some(Vec(p(NExtMMIOAXIChannels), Clock(INPUT))) else None
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val mmio_rst = if (p(AsyncMMIOChannels)) Some(Vec(p(NExtMMIOAXIChannels), Bool (INPUT))) else None
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val mmio_axi = Vec(p(NExtMMIOAXIChannels), new NastiIO)
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val mmio_ahb = Vec(p(NExtMMIOAHBChannels), new HastiMasterIO)
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val mmio_tl = Vec(p(NExtMMIOTLChannels), new ClientUncachedTileLinkIO()(outermostMMIOParams))
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val debug_clk = if (p(AsyncDebugBus)) Some(Clock(INPUT)) else None
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val debug_rst = if (p(AsyncDebugBus)) Some(Bool(INPUT)) else None
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val debug = new DebugBusIO()(p).flip
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val extra = p(ExtraTopPorts)(p)
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}
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object TopUtils {
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// Connect two Nasti interfaces with queues in-between
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def connectNasti(outer: NastiIO, inner: NastiIO)(implicit p: Parameters) {
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val mifDataBeats = p(MIFDataBeats)
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outer.ar <> Queue(inner.ar, 1)
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outer.aw <> Queue(inner.aw, 1)
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outer.w <> Queue(inner.w)
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inner.r <> Queue(outer.r)
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inner.b <> Queue(outer.b, 1)
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}
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def connectTilelinkNasti(nasti: NastiIO, tl: ClientUncachedTileLinkIO)(implicit p: Parameters) = {
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val conv = Module(new NastiIOTileLinkIOConverter())
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conv.io.tl <> tl
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TopUtils.connectNasti(nasti, conv.io.nasti)
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}
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def connectTilelinkAhb(ahb: HastiMasterIO, tl: ClientUncachedTileLinkIO)(implicit p: Parameters) = {
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val bridge = Module(new AHBBridge(true))
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bridge.io.tl <> tl
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bridge.io.ahb
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}
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def connectTilelink(
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outer: ClientUncachedTileLinkIO, inner: ClientUncachedTileLinkIO)(implicit p: Parameters) = {
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outer.acquire <> Queue(inner.acquire)
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inner.grant <> Queue(outer.grant)
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}
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}
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/** Top-level module for the chip */
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//TODO: Remove this wrapper once multichannel DRAM controller is provided
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class Top(topParams: Parameters) extends Module with HasTopLevelParameters {
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implicit val p = topParams
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val io = new TopIO
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// Build an Uncore and a set of Tiles
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val tileResets = Wire(Vec(nTiles, Bool()))
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val tileList = p(BuildTiles).zip(tileResets).map {
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case (tile, rst) => tile(rst, p)
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}
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val nCachedPorts = tileList.map(tile => tile.io.cached.size).reduce(_ + _)
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val nUncachedPorts = tileList.map(tile => tile.io.uncached.size).reduce(_ + _)
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val innerTLParams = p.alterPartial({
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case HastiId => "TL"
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case TLId => "L1toL2"
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case NCachedTileLinkPorts => nCachedPorts
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case NUncachedTileLinkPorts => nUncachedPorts
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})
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val uncore = Module(new Uncore()(innerTLParams))
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(uncore.io.prci, tileResets, tileList).zipped.foreach {
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case (prci, rst, tile) =>
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rst := prci.reset
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tile.io.prci <> prci
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}
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// Connect the uncore to the tile memory ports, HostIO and MemIO
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uncore.io.tiles_cached <> tileList.map(_.io.cached).flatten
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uncore.io.tiles_uncached <> tileList.map(_.io.uncached).flatten
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uncore.io.interrupts <> io.interrupts
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uncore.io.debugBus <>
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(if (p(AsyncDebugBus))
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AsyncDebugBusFrom(io.debug_clk.get, io.debug_rst.get, io.debug)
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else io.debug)
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def asyncAxiTo(clocks: Seq[Clock], resets: Seq[Bool], inner_axis: Seq[NastiIO]): Seq[NastiIO] =
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(clocks, resets, inner_axis).zipped.map {
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case (clk, rst, in_axi) => AsyncNastiTo(clk, rst, in_axi)
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}
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def asyncAxiFrom(clocks: Seq[Clock], resets: Seq[Bool], outer_axis: Seq[NastiIO]): Seq[NastiIO] =
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(clocks, resets, outer_axis).zipped.map {
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case (clk, rst, out_axi) => AsyncNastiFrom(clk, rst, out_axi)
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}
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io.mmio_axi <>
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(if (p(AsyncMMIOChannels))
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asyncAxiTo(io.mmio_clk.get, io.mmio_rst.get, uncore.io.mmio_axi)
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else uncore.io.mmio_axi)
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io.mmio_ahb <> uncore.io.mmio_ahb
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io.mmio_tl <> uncore.io.mmio_tl
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io.mem_axi <>
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(if (p(AsyncMemChannels))
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asyncAxiTo(io.mem_clk.get, io.mem_rst.get, uncore.io.mem_axi)
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else uncore.io.mem_axi)
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io.mem_ahb <> uncore.io.mem_ahb
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io.mem_tl <> uncore.io.mem_tl
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uncore.io.bus_axi <>
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(if (p(AsyncBusChannels))
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asyncAxiFrom(io.bus_clk.get, io.bus_rst.get, io.bus_axi)
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else io.bus_axi)
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io.extra <> uncore.io.extra
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}
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/** Wrapper around everything that isn't a Tile.
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*
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* Usually this is clocked and/or place-and-routed separately from the Tiles.
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*/
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class Uncore(implicit val p: Parameters) extends Module
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with HasTopLevelParameters {
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val io = new Bundle {
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val mem_axi = Vec(nMemAXIChannels, new NastiIO)
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val mem_ahb = Vec(nMemAHBChannels, new HastiMasterIO)
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val mem_tl = Vec(nMemTLChannels, new ClientUncachedTileLinkIO()(outermostParams))
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val tiles_cached = Vec(nCachedTilePorts, new ClientTileLinkIO).flip
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val tiles_uncached = Vec(nUncachedTilePorts, new ClientUncachedTileLinkIO).flip
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val prci = Vec(nTiles, new PRCITileIO).asOutput
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val bus_axi = Vec(p(NExtBusAXIChannels), new NastiIO).flip
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val mmio_axi = Vec(p(NExtMMIOAXIChannels), new NastiIO)
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val mmio_ahb = Vec(p(NExtMMIOAHBChannels), new HastiMasterIO)
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val mmio_tl = Vec(p(NExtMMIOTLChannels), new ClientUncachedTileLinkIO()(outermostMMIOParams))
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val interrupts = Vec(p(NExtInterrupts), Bool()).asInput
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val debugBus = new DebugBusIO()(p).flip
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val extra = p(ExtraTopPorts)(p)
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}
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val outmemsys = if (nCachedTilePorts + nUncachedTilePorts > 0)
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Module(new OuterMemorySystem) // NoC, LLC and SerDes
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else Module(new DummyOuterMemorySystem)
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outmemsys.io.incoherent foreach (_ := false)
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outmemsys.io.tiles_uncached <> io.tiles_uncached
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outmemsys.io.tiles_cached <> io.tiles_cached
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buildMMIONetwork(p.alterPartial({case TLId => "L2toMMIO"}))
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io.mem_axi <> outmemsys.io.mem_axi
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io.mem_ahb <> outmemsys.io.mem_ahb
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io.mem_tl <> outmemsys.io.mem_tl
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outmemsys.io.bus_axi <> io.bus_axi
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def connectExternalMMIO(ports: Seq[ClientUncachedTileLinkIO])(implicit p: Parameters) {
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val mmio_axi_start = 0
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val mmio_axi_end = mmio_axi_start + p(NExtMMIOAXIChannels)
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val mmio_ahb_start = mmio_axi_end
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val mmio_ahb_end = mmio_ahb_start + p(NExtMMIOAHBChannels)
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val mmio_tl_start = mmio_ahb_end
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val mmio_tl_end = mmio_tl_start + p(NExtMMIOTLChannels)
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require (mmio_tl_end == ports.size)
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for (i <- 0 until ports.size) {
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if (mmio_axi_start <= i && i < mmio_axi_end) {
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TopUtils.connectTilelinkNasti(io.mmio_axi(i-mmio_axi_start), ports(i))
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} else if (mmio_ahb_start <= i && i < mmio_ahb_end) {
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val ahbBridge = Module(new AHBBridge(true))
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io.mmio_ahb(i-mmio_ahb_start) <> ahbBridge.io.ahb
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ahbBridge.io.tl <> ports(i)
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} else if (mmio_tl_start <= i && i < mmio_tl_end) {
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TopUtils.connectTilelink(io.mmio_tl(i-mmio_tl_start), ports(i))
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} else {
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require(false, "Unconnected external MMIO port")
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}
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}
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}
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def makeBootROM()(implicit p: Parameters) = {
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val romdata = Files.readAllBytes(Paths.get(p(BootROMFile)))
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val rom = ByteBuffer.wrap(romdata)
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rom.order(ByteOrder.LITTLE_ENDIAN)
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// for now, have the reset vector jump straight to memory
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val resetToMemDist = p(GlobalAddrMap)("mem").start - p(ResetVector)
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require(resetToMemDist == (resetToMemDist.toInt >> 12 << 12))
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val configStringAddr = p(ResetVector).toInt + rom.capacity
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require(rom.getInt(12) == 0,
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"Config string address position should not be occupied by code")
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rom.putInt(12, configStringAddr)
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rom.array() ++ p(ConfigString).toSeq
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}
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def buildMMIONetwork(implicit p: Parameters) = {
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val ioAddrMap = p(GlobalAddrMap).subMap("io")
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val mmioNetwork = Module(new TileLinkRecursiveInterconnect(1, ioAddrMap))
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mmioNetwork.io.in.head <> outmemsys.io.mmio
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val plic = Module(new PLIC(p(PLICKey)))
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plic.io.tl <> mmioNetwork.port("int:plic")
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for (i <- 0 until io.interrupts.size) {
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val gateway = Module(new LevelGateway)
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gateway.io.interrupt := io.interrupts(i)
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plic.io.devices(i) <> gateway.io.plic
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}
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val debugModule = Module(new DebugModule)
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debugModule.io.tl <> mmioNetwork.port("int:debug")
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debugModule.io.db <> io.debugBus
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val prci = Module(new PRCI)
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prci.io.tl <> mmioNetwork.port("int:prci")
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io.prci := prci.io.tiles
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prci.io.rtcTick := Counter(p(RTCPeriod)).inc() // placeholder for real RTC
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for (i <- 0 until nTiles) {
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prci.io.interrupts(i).meip := plic.io.harts(plic.cfg.context(i, 'M'))
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if (p(UseVM))
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prci.io.interrupts(i).seip := plic.io.harts(plic.cfg.context(i, 'S'))
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prci.io.interrupts(i).debug := debugModule.io.debugInterrupts(i)
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io.prci(i).reset := reset
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}
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val bootROM = Module(new ROMSlave(makeBootROM()))
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bootROM.io <> mmioNetwork.port("int:bootrom")
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for (device <- p(ExtraDevices)) {
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device.builder(mmioNetwork.port("int:" + device.addrMapEntry.name), io.extra, p)
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}
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val ext = p(ExtMMIOPorts).entries.map(port => TileLinkWidthAdapter(mmioNetwork.port(port.name), "MMIO_Outermost"))
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connectExternalMMIO(ext)(outermostMMIOParams)
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}
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}
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abstract class AbstractOuterMemorySystem(implicit val p: Parameters)
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extends Module with HasTopLevelParameters {
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val io = new Bundle {
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val tiles_cached = Vec(nCachedTilePorts, new ClientTileLinkIO).flip
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val tiles_uncached = Vec(nUncachedTilePorts, new ClientUncachedTileLinkIO).flip
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val incoherent = Vec(nCachedTilePorts, Bool()).asInput
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val mem_axi = Vec(nMemAXIChannels, new NastiIO)
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val mem_ahb = Vec(nMemAHBChannels, new HastiMasterIO)
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val mem_tl = Vec(nMemTLChannels, new ClientUncachedTileLinkIO()(outermostParams))
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val bus_axi = Vec(p(NExtBusAXIChannels), new NastiIO).flip
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val mmio = new ClientUncachedTileLinkIO()(p.alterPartial({case TLId => "L2toMMIO"}))
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}
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}
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/** Use in place of OuterMemorySystem if there are no clients to connect. */
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class DummyOuterMemorySystem(implicit p: Parameters) extends AbstractOuterMemorySystem()(p) {
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require(nCachedTilePorts + nUncachedTilePorts == 0)
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io.mem_axi.foreach { axi =>
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axi.ar.valid := Bool(false)
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axi.aw.valid := Bool(false)
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axi.w.valid := Bool(false)
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axi.r.ready := Bool(false)
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axi.b.ready := Bool(false)
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}
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io.mem_ahb.foreach { ahb =>
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ahb.htrans := UInt(0)
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ahb.hmastlock := Bool(false)
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ahb.hwrite := Bool(false)
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ahb.haddr := UInt(0)
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ahb.hburst := UInt(0)
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ahb.hsize := UInt(0)
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ahb.hprot := UInt(0)
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}
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io.mem_tl.foreach { tl =>
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tl.acquire.valid := Bool(false)
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tl.grant.ready := Bool(false)
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}
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io.mmio.acquire.valid := Bool(false)
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io.mmio.grant.ready := Bool(false)
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}
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/** The whole outer memory hierarchy, including a NoC, some kind of coherence
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* manager agent, and a converter from TileLink to MemIO.
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*/
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class OuterMemorySystem(implicit p: Parameters) extends AbstractOuterMemorySystem()(p) {
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// Create a simple L1toL2 NoC between the tiles and the banks of outer memory
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// Cached ports are first in client list, making sharerToClientId just an indentity function
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// addrToBank is sed to hash physical addresses (of cache blocks) to banks (and thereby memory channels)
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def sharerToClientId(sharerId: UInt) = sharerId
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def addrToBank(addr: UInt): UInt = {
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val isMemory = p(GlobalAddrMap).isInRegion("mem", addr << log2Up(p(CacheBlockBytes)))
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Mux(isMemory,
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if (nBanks > 1) addr(lsb + log2Up(nBanks) - 1, lsb) else UInt(0),
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UInt(nBanks))
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}
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val preBuffering = TileLinkDepths(1,1,2,2,0)
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val l1tol2net = Module(new PortedTileLinkCrossbar(addrToBank, sharerToClientId, preBuffering))
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// Create point(s) of coherence serialization
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val managerEndpoints = List.tabulate(nBanks){id => p(BuildL2CoherenceManager)(id, p)}
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managerEndpoints.foreach { _.incoherent := io.incoherent }
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|
val mmioManager = Module(new MMIOTileLinkManager()(p.alterPartial({
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|
case TLId => "L1toL2"
|
|
case InnerTLId => "L1toL2"
|
|
case OuterTLId => "L2toMMIO"
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|
})))
|
|
io.mmio <> mmioManager.io.outer
|
|
|
|
val bus_in = io.bus_axi.map { ext_nasti =>
|
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val converter = Module(new TileLinkIONastiIOConverter)
|
|
converter.io.nasti <> ext_nasti
|
|
converter.io.tl
|
|
}
|
|
|
|
// Wire the tiles to the TileLink client ports of the L1toL2 network,
|
|
// and coherence manager(s) to the other side
|
|
l1tol2net.io.clients_cached <> io.tiles_cached
|
|
l1tol2net.io.clients_uncached <> io.tiles_uncached ++ bus_in
|
|
l1tol2net.io.managers <> managerEndpoints.map(_.innerTL) :+ mmioManager.io.inner
|
|
|
|
// Create a converter between TileLinkIO and MemIO for each channel
|
|
val outerTLParams = p.alterPartial({ case TLId => "L2toMC" })
|
|
val outermostTLParams = p.alterPartial({case TLId => "Outermost"})
|
|
val backendBuffering = TileLinkDepths(0,0,0,0,0)
|
|
|
|
// TODO: the code to print this stuff should live somewhere else
|
|
println("Generated Address Map")
|
|
for ((name, region) <- p(GlobalAddrMap).flatten) {
|
|
println(f"\t$name%s ${region.start}%x - ${region.start + region.size - 1}%x")
|
|
}
|
|
println("Generated Configuration String")
|
|
println(new String(p(ConfigString)))
|
|
|
|
val mem_ic = Module(new TileLinkMemoryInterconnect(nBanksPerMemChannel, nMemChannels)(outermostTLParams))
|
|
|
|
for ((bank, icPort) <- managerEndpoints zip mem_ic.io.in) {
|
|
val unwrap = Module(new ClientTileLinkIOUnwrapper()(outerTLParams))
|
|
unwrap.io.in <> ClientTileLinkEnqueuer(bank.outerTL, backendBuffering)(outerTLParams)
|
|
TileLinkWidthAdapter(icPort, unwrap.io.out)
|
|
}
|
|
|
|
for ((nasti, tl) <- io.mem_axi zip mem_ic.io.out) {
|
|
TopUtils.connectTilelinkNasti(nasti, tl)(outermostTLParams)
|
|
// Memory cache type should be normal non-cacheable bufferable
|
|
// TODO why is this happening here? Would 0000 (device) be OK instead?
|
|
nasti.ar.bits.cache := UInt("b0011")
|
|
nasti.aw.bits.cache := UInt("b0011")
|
|
}
|
|
|
|
// Abuse the fact that zip takes the shorter of the two lists
|
|
for ((ahb, tl) <- io.mem_ahb zip mem_ic.io.out) {
|
|
val bridge = Module(new AHBBridge(false)) // no atomics
|
|
ahb <> bridge.io.ahb
|
|
bridge.io.tl <> tl
|
|
}
|
|
|
|
for ((mem_tl, tl) <- io.mem_tl zip mem_ic.io.out) {
|
|
TopUtils.connectTilelink(mem_tl, tl)
|
|
}
|
|
}
|