632 lines
24 KiB
Scala
632 lines
24 KiB
Scala
// See LICENSE for license details.
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package rocketchip
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import Chisel._
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import junctions._
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import uncore.tilelink._
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import uncore.coherence._
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import uncore.agents._
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import uncore.devices._
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import uncore.converters._
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import rocket._
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import rocket.Util._
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import groundtest._
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import scala.math.max
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import scala.collection.mutable.{LinkedHashSet, ListBuffer}
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import DefaultTestSuites._
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import cde.{Parameters, Config, Dump, Knob, CDEMatchError}
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object ConfigUtils {
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def max_int(values: Int*): Int = {
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values.reduce((a, b) => max(a, b))
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}
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}
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import ConfigUtils._
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class BaseConfig extends Config (
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topDefinitions = { (pname,site,here) =>
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type PF = PartialFunction[Any,Any]
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def findBy(sname:Any):Any = here[PF](site[Any](sname))(pname)
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lazy val internalIOAddrMap: AddrMap = {
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val entries = collection.mutable.ArrayBuffer[AddrMapEntry]()
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entries += AddrMapEntry("debug", MemSize(4096, MemAttr(AddrMapProt.RWX)))
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entries += AddrMapEntry("bootrom", MemSize(4096, MemAttr(AddrMapProt.RX)))
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entries += AddrMapEntry("plic", MemRange(0x40000000, 0x4000000, MemAttr(AddrMapProt.RW)))
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entries += AddrMapEntry("prci", MemSize(0x4000000, MemAttr(AddrMapProt.RW)))
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entries ++= site(ExtraDevices).map(_.addrMapEntry)
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new AddrMap(entries)
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}
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lazy val globalAddrMap = {
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val memBase = 0x80000000L
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val memSize = 0x10000000L
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val io = new AddrMap(AddrMapEntry("int", internalIOAddrMap) +: site(ExtMMIOPorts).entries)
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val addrMap = AddrMap(
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AddrMapEntry("io", io),
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AddrMapEntry("mem", MemRange(memBase, memSize, MemAttr(AddrMapProt.RWX, true))))
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Dump("MEM_BASE", addrMap("mem").start)
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Dump("MEM_SIZE", memSize)
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addrMap
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}
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def makeConfigString() = {
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val addrMap = globalAddrMap
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val plicAddr = addrMap("io:int:plic").start
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val prciAddr = addrMap("io:int:prci").start
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val plicInfo = site(PLICKey)
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val xLen = site(XLen)
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val res = new StringBuilder
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res append "plic {\n"
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res append s" priority 0x${plicAddr.toString(16)};\n"
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res append s" pending 0x${(plicAddr + plicInfo.pendingBase).toString(16)};\n"
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res append s" ndevs ${plicInfo.nDevices};\n"
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res append "};\n"
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res append "rtc {\n"
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res append s" addr 0x${(prciAddr + PRCI.time).toString(16)};\n"
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res append "};\n"
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res append "ram {\n"
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res append " 0 {\n"
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res append s" addr 0x${addrMap("mem").start.toString(16)};\n"
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res append s" size 0x${addrMap("mem").size.toString(16)};\n"
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res append " };\n"
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res append "};\n"
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res append "core {\n"
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for (i <- 0 until site(NTiles)) {
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val isa = s"rv${site(XLen)}im${if (site(UseAtomics)) "a" else ""}${if (site(UseFPU)) "fd" else ""}"
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res append s" $i {\n"
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res append " 0 {\n"
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res append s" isa $isa;\n"
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res append s" timecmp 0x${(prciAddr + PRCI.timecmp(i)).toString(16)};\n"
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res append s" ipi 0x${(prciAddr + PRCI.msip(i)).toString(16)};\n"
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res append s" plic {\n"
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res append s" m {\n"
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res append s" ie 0x${(plicAddr + plicInfo.enableAddr(i, 'M')).toString(16)};\n"
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res append s" thresh 0x${(plicAddr + plicInfo.threshAddr(i, 'M')).toString(16)};\n"
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res append s" claim 0x${(plicAddr + plicInfo.claimAddr(i, 'M')).toString(16)};\n"
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res append s" };\n"
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if (site(UseVM)) {
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res append s" s {\n"
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res append s" ie 0x${(plicAddr + plicInfo.enableAddr(i, 'S')).toString(16)};\n"
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res append s" thresh 0x${(plicAddr + plicInfo.threshAddr(i, 'S')).toString(16)};\n"
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res append s" claim 0x${(plicAddr + plicInfo.claimAddr(i, 'S')).toString(16)};\n"
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res append s" };\n"
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}
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res append s" };\n"
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res append " };\n"
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res append " };\n"
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}
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for (device <- site(ExtraDevices)) {
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val deviceName = device.addrMapEntry.name
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val deviceRegion = addrMap("io:int:" + deviceName)
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res.append(device.makeConfigString(deviceRegion))
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}
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res append "};\n"
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res append '\u0000'
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res.toString.getBytes
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}
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lazy val innerDataBits = 64
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lazy val innerDataBeats = (8 * site(CacheBlockBytes)) / innerDataBits
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pname match {
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//Memory Parameters
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case PAddrBits => 32
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case PgIdxBits => 12
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case PgLevels => if (site(XLen) == 64) 3 /* Sv39 */ else 2 /* Sv32 */
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case PgLevelBits => site(PgIdxBits) - log2Up(site(XLen)/8)
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case VPNBits => site(PgLevels) * site(PgLevelBits)
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case PPNBits => site(PAddrBits) - site(PgIdxBits)
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case VAddrBits => site(VPNBits) + site(PgIdxBits)
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case ASIdBits => 7
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case MIFTagBits => Dump("MIF_TAG_BITS", 5)
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case MIFDataBits => Dump("MIF_DATA_BITS", 64)
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case MIFAddrBits => Dump("MIF_ADDR_BITS",
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site(PAddrBits) - site(CacheBlockOffsetBits))
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case MIFDataBeats => site(CacheBlockBytes) * 8 / site(MIFDataBits)
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case NastiKey => {
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Dump("MEM_STRB_BITS", site(MIFDataBits) / 8)
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NastiParameters(
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dataBits = Dump("MEM_DATA_BITS", site(MIFDataBits)),
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addrBits = Dump("MEM_ADDR_BITS", site(PAddrBits)),
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idBits = Dump("MEM_ID_BITS", site(MIFTagBits)))
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}
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//Params used by all caches
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case NSets => findBy(CacheName)
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case NWays => findBy(CacheName)
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case RowBits => findBy(CacheName)
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case NTLBEntries => findBy(CacheName)
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case CacheIdBits => findBy(CacheName)
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case SplitMetadata => findBy(CacheName)
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case "L1I" => {
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case NSets => Knob("L1I_SETS") //64
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case NWays => Knob("L1I_WAYS") //4
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case RowBits => site(TLKey("L1toL2")).dataBitsPerBeat
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case NTLBEntries => 8
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case CacheIdBits => 0
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case SplitMetadata => false
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}:PF
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case "L1D" => {
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case NSets => Knob("L1D_SETS") //64
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case NWays => Knob("L1D_WAYS") //4
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case RowBits => site(TLKey("L1toL2")).dataBitsPerBeat
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case NTLBEntries => 8
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case CacheIdBits => 0
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case SplitMetadata => false
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}:PF
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case ECCCode => None
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case Replacer => () => new RandomReplacement(site(NWays))
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case AmoAluOperandBits => site(XLen)
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//L1InstCache
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case BtbKey => BtbParameters()
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//L1DataCache
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case WordBits => site(XLen)
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case StoreDataQueueDepth => 17
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case ReplayQueueDepth => 16
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case NMSHRs => Knob("L1D_MSHRS")
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case LRSCCycles => 32
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//L2 Memory System Params
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case NAcquireTransactors => 7
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case L2StoreDataQueueDepth => 1
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case L2DirectoryRepresentation => new NullRepresentation(site(NTiles))
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case BuildL2CoherenceManager => (id: Int, p: Parameters) =>
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Module(new L2BroadcastHub()(p.alterPartial({
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case InnerTLId => "L1toL2"
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case OuterTLId => "L2toMC" })))
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case NCachedTileLinkPorts => 1
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case NUncachedTileLinkPorts => 1
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//Tile Constants
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case BuildTiles => {
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val (rvi, rvu) =
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if (site(XLen) == 64) ((if (site(UseVM)) rv64i else rv64pi), rv64u)
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else ((if (site(UseVM)) rv32i else rv32pi), rv32u)
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TestGeneration.addSuites(rvi.map(_("p")))
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TestGeneration.addSuites((if(site(UseVM)) List("v") else List()).flatMap(env => rvu.map(_(env))))
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TestGeneration.addSuite(if (site(UseVM)) benchmarks else emptyBmarks)
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List.fill(site(NTiles)){ (r: Bool, p: Parameters) =>
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Module(new RocketTile(resetSignal = r)(p.alterPartial({
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case TLId => "L1toL2"
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case NUncachedTileLinkPorts => 1 + site(RoccNMemChannels)
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})))
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}
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}
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case BuildRoCC => Nil
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case RoccNMemChannels => site(BuildRoCC).map(_.nMemChannels).foldLeft(0)(_ + _)
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case RoccNPTWPorts => site(BuildRoCC).map(_.nPTWPorts).foldLeft(0)(_ + _)
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case RoccNCSRs => site(BuildRoCC).map(_.csrs.size).foldLeft(0)(_ + _)
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//Rocket Core Constants
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case FetchWidth => if (site(UseCompressed)) 2 else 1
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case RetireWidth => 1
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case UseVM => true
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case UseUser => true
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case UseDebug => true
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case AsyncDebugBus => false
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case NBreakpoints => 1
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case UsePerfCounters => true
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case FastLoadWord => true
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case FastLoadByte => false
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case MulUnroll => 8
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case DivEarlyOut => true
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case XLen => 64
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case UseFPU => {
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val env = if(site(UseVM)) List("p","v") else List("p")
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TestGeneration.addSuite(rv32udBenchmarks)
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if(site(FDivSqrt)) {
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TestGeneration.addSuites(env.map(rv64uf))
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TestGeneration.addSuites(env.map(rv64ud))
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} else {
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TestGeneration.addSuites(env.map(rv64ufNoDiv))
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TestGeneration.addSuites(env.map(rv64udNoDiv))
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}
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true
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}
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case UseAtomics => {
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val env = if(site(UseVM)) List("p","v") else List("p")
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TestGeneration.addSuites(env.map(if (site(XLen) == 64) rv64ua else rv32ua))
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true
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}
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case UseCompressed => {
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val env = if(site(UseVM)) List("p","v") else List("p")
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TestGeneration.addSuites(env.map(if (site(XLen) == 64) rv64uc else rv32uc))
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true
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}
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case NExtInterrupts => 2
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case AsyncMMIOChannels => false
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case ExtraDevices => Nil
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case ExtraTopPorts => (p: Parameters) => new Bundle
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case ExtMMIOPorts => AddrMap()
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/*
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AddrMap(
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AddrMapEntry("cfg", MemRange(0x50000000L, 0x04000000L, MemAttr(AddrMapProt.RW))),
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AddrMapEntry("ext", MemRange(0x60000000L, 0x20000000L, MemAttr(AddrMapProt.RWX))))
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*/
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case NExtMMIOAXIChannels => 0
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case NExtMMIOAHBChannels => 0
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case NExtMMIOTLChannels => 0
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case AsyncBusChannels => false
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case NExtBusAXIChannels => 0
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case PLICKey => PLICConfig(site(NTiles), site(UseVM), site(NExtInterrupts), 0)
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case DMKey => new DefaultDebugModuleConfig(site(NTiles), site(XLen))
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case FDivSqrt => true
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case SFMALatency => 2
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case DFMALatency => 3
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case CoreInstBits => if (site(UseCompressed)) 16 else 32
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case CoreDataBits => site(XLen)
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case NCustomMRWCSRs => 0
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case ResetVector => BigInt(0x1000)
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case MtvecInit => BigInt(0x1010)
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case MtvecWritable => true
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//Uncore Paramters
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case RTCPeriod => 100 // gives 10 MHz RTC assuming 1 GHz uncore clock
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case LNEndpoints => site(TLKey(site(TLId))).nManagers + site(TLKey(site(TLId))).nClients
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case LNHeaderBits => log2Ceil(site(TLKey(site(TLId))).nManagers) +
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log2Up(site(TLKey(site(TLId))).nClients)
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case HastiId => "Ext"
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case HastiKey("TL") =>
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HastiParameters(
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addrBits = site(PAddrBits),
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dataBits = site(TLKey(site(TLId))).dataBits / site(TLKey(site(TLId))).dataBeats)
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case HastiKey("Ext") =>
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HastiParameters(
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addrBits = site(PAddrBits),
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dataBits = site(XLen))
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case TLKey("L1toL2") => {
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val useMEI = site(NTiles) <= 1 && site(NCachedTileLinkPorts) <= 1
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TileLinkParameters(
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coherencePolicy = (
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if (useMEI) new MEICoherence(site(L2DirectoryRepresentation))
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else new MESICoherence(site(L2DirectoryRepresentation))),
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nManagers = site(NBanksPerMemoryChannel)*site(NMemoryChannels) + 1 /* MMIO */,
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nCachingClients = site(NCachedTileLinkPorts),
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nCachelessClients = site(NExtBusAXIChannels) + site(NUncachedTileLinkPorts),
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maxClientXacts = max_int(
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// L1 cache
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site(NMSHRs) + 1 /* IOMSHR */,
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// RoCC
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if (site(BuildRoCC).isEmpty) 1 else site(RoccMaxTaggedMemXacts)),
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maxClientsPerPort = if (site(BuildRoCC).isEmpty) 1 else 2,
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maxManagerXacts = site(NAcquireTransactors) + 2,
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dataBeats = innerDataBeats,
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dataBits = site(CacheBlockBytes)*8)
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}
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case TLKey("L2toMC") =>
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TileLinkParameters(
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coherencePolicy = new MEICoherence(
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new NullRepresentation(site(NBanksPerMemoryChannel))),
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nManagers = 1,
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nCachingClients = site(NBanksPerMemoryChannel),
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nCachelessClients = 0,
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maxClientXacts = 1,
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maxClientsPerPort = site(NAcquireTransactors) + 2,
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maxManagerXacts = 1,
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dataBeats = innerDataBeats,
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dataBits = site(CacheBlockBytes)*8)
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case TLKey("Outermost") => site(TLKey("L2toMC")).copy(
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maxClientXacts = site(NAcquireTransactors) + 2,
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maxClientsPerPort = site(NBanksPerMemoryChannel),
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dataBeats = site(MIFDataBeats))
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case TLKey("L2toMMIO") => {
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TileLinkParameters(
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coherencePolicy = new MICoherence(
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new NullRepresentation(site(NBanksPerMemoryChannel))),
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nManagers = globalAddrMap.subMap("io").flatten.size,
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nCachingClients = 0,
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nCachelessClients = 1,
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maxClientXacts = 4,
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maxClientsPerPort = 1,
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maxManagerXacts = 1,
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dataBeats = innerDataBeats,
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dataBits = site(CacheBlockBytes) * 8)
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}
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case BootROMFile => "./bootrom/bootrom.img"
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case TLKey("MMIO_Outermost") => site(TLKey("L2toMMIO")).copy(dataBeats = site(MIFDataBeats))
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case NTiles => Knob("NTILES")
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case AsyncMemChannels => false
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case NMemoryChannels => Dump("N_MEM_CHANNELS", 1)
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case TMemoryChannels => BusType.AXI
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case NBanksPerMemoryChannel => Knob("NBANKS_PER_MEM_CHANNEL")
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case NOutstandingMemReqsPerChannel => site(NBanksPerMemoryChannel)*(site(NAcquireTransactors)+2)
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case BankIdLSB => 0
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case CacheBlockBytes => Dump("CACHE_BLOCK_BYTES", 64)
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case CacheBlockOffsetBits => log2Up(here(CacheBlockBytes))
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case ConfigString => makeConfigString()
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case GlobalAddrMap => globalAddrMap
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case EnableL2Logging => false
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case ExportGroundTestStatus => false
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case RegressionTestNames => LinkedHashSet(
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"rv64ud-v-fcvt",
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"rv64ud-p-fdiv",
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"rv64ud-v-fadd",
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"rv64uf-v-fadd",
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"rv64um-v-mul",
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"rv64mi-p-breakpoint",
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"rv64uc-v-rvc",
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"rv64ud-v-structural",
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"rv64si-p-wfi",
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"rv64um-v-divw",
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"rv64ua-v-lrsc",
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"rv64ui-v-fence_i",
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"rv64ud-v-fcvt_w",
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"rv64uf-v-fmin",
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"rv64ui-v-sb",
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"rv64ua-v-amomax_d",
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"rv64ud-v-move",
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"rv64ud-v-fclass",
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"rv64ua-v-amoand_d",
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"rv64ua-v-amoxor_d",
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"rv64si-p-sbreak",
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"rv64ud-v-fmadd",
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"rv64uf-v-ldst",
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"rv64um-v-mulh",
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"rv64si-p-dirty")
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case _ => throw new CDEMatchError
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}},
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knobValues = {
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case "NTILES" => 1
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case "NBANKS_PER_MEM_CHANNEL" => 1
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case "L1D_MSHRS" => 2
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case "L1D_SETS" => 64
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case "L1D_WAYS" => 4
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case "L1I_SETS" => 64
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case "L1I_WAYS" => 4
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case _ => throw new CDEMatchError
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}
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)
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class DefaultConfig extends Config(new WithBlockingL1 ++ new BaseConfig)
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class WithNCores(n: Int) extends Config(
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knobValues = { case"NTILES" => n; case _ => throw new CDEMatchError })
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class WithNBanksPerMemChannel(n: Int) extends Config(
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knobValues = {
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case "NBANKS_PER_MEM_CHANNEL" => n;
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case _ => throw new CDEMatchError
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})
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class WithNMemoryChannels(n: Int) extends Config(
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(pname,site,here) => pname match {
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case NMemoryChannels => Dump("N_MEM_CHANNELS", n)
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case _ => throw new CDEMatchError
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}
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)
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class WithL2Cache extends Config(
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(pname,site,here) => pname match {
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case "L2_CAPACITY_IN_KB" => Knob("L2_CAPACITY_IN_KB")
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case "L2Bank" => {
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case NSets => (((here[Int]("L2_CAPACITY_IN_KB")*1024) /
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site(CacheBlockBytes)) /
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(site(NBanksPerMemoryChannel)*site(NMemoryChannels))) /
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site(NWays)
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case NWays => Knob("L2_WAYS")
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case RowBits => site(TLKey(site(TLId))).dataBitsPerBeat
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case CacheIdBits => log2Ceil(site(NMemoryChannels) * site(NBanksPerMemoryChannel))
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case SplitMetadata => Knob("L2_SPLIT_METADATA")
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}: PartialFunction[Any,Any]
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case NAcquireTransactors => 2
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case NSecondaryMisses => 4
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case L2DirectoryRepresentation => new FullRepresentation(site(NTiles))
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case BuildL2CoherenceManager => (id: Int, p: Parameters) =>
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Module(new L2HellaCacheBank()(p.alterPartial({
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case CacheId => id
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case CacheName => "L2Bank"
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case InnerTLId => "L1toL2"
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case OuterTLId => "L2toMC"})))
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case L2Replacer => () => new SeqRandom(site(NWays))
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case _ => throw new CDEMatchError
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},
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knobValues = { case "L2_WAYS" => 8; case "L2_CAPACITY_IN_KB" => 2048; case "L2_SPLIT_METADATA" => false; case _ => throw new CDEMatchError }
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)
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|
|
|
class WithBufferlessBroadcastHub extends Config(
|
|
(pname, site, here) => pname match {
|
|
case BuildL2CoherenceManager => (id: Int, p: Parameters) =>
|
|
Module(new BufferlessBroadcastHub()(p.alterPartial({
|
|
case InnerTLId => "L1toL2"
|
|
case OuterTLId => "L2toMC" })))
|
|
})
|
|
|
|
/**
|
|
* WARNING!!! IGNORE AT YOUR OWN PERIL!!!
|
|
*
|
|
* There is a very restrictive set of conditions under which the stateless
|
|
* bridge will function properly. There can only be a single tile. This tile
|
|
* MUST use the blocking data cache (L1D_MSHRS == 0) and MUST NOT have an
|
|
* uncached channel capable of writes (i.e. a RoCC accelerator).
|
|
*
|
|
* This is because the stateless bridge CANNOT generate probes, so if your
|
|
* system depends on coherence between channels in any way,
|
|
* DO NOT use this configuration.
|
|
*/
|
|
class WithStatelessBridge extends Config (
|
|
topDefinitions = (pname, site, here) => pname match {
|
|
case BuildL2CoherenceManager => (id: Int, p: Parameters) =>
|
|
Module(new ManagerToClientStatelessBridge()(p.alterPartial({
|
|
case InnerTLId => "L1toL2"
|
|
case OuterTLId => "L2toMC" })))
|
|
},
|
|
knobValues = {
|
|
case "L1D_MSHRS" => 0
|
|
case _ => throw new CDEMatchError
|
|
}
|
|
)
|
|
|
|
class WithPLRU extends Config(
|
|
(pname, site, here) => pname match {
|
|
case L2Replacer => () => new SeqPLRU(site(NSets), site(NWays))
|
|
case _ => throw new CDEMatchError
|
|
})
|
|
|
|
class WithL2Capacity(size_kb: Int) extends Config(
|
|
knobValues = {
|
|
case "L2_CAPACITY_IN_KB" => size_kb
|
|
case _ => throw new CDEMatchError
|
|
})
|
|
|
|
class WithNL2Ways(n: Int) extends Config(
|
|
knobValues = {
|
|
case "L2_WAYS" => n
|
|
case _ => throw new CDEMatchError
|
|
})
|
|
|
|
class DefaultL2Config extends Config(new WithL2Cache ++ new BaseConfig)
|
|
class DefaultL2FPGAConfig extends Config(
|
|
new WithL2Capacity(64) ++ new WithL2Cache ++ new DefaultFPGAConfig)
|
|
|
|
class DefaultBufferlessConfig extends Config(
|
|
new WithBufferlessBroadcastHub ++ new BaseConfig)
|
|
|
|
class PLRUL2Config extends Config(new WithPLRU ++ new DefaultL2Config)
|
|
|
|
class WithRV32 extends Config(
|
|
(pname,site,here) => pname match {
|
|
case XLen => 32
|
|
case UseVM => false
|
|
case UseUser => false
|
|
case UseAtomics => false
|
|
case UseFPU => false
|
|
case RegressionTestNames => LinkedHashSet(
|
|
"rv32mi-p-ma_addr",
|
|
"rv32mi-p-csr",
|
|
"rv32ui-p-sh",
|
|
"rv32ui-p-lh",
|
|
"rv32mi-p-sbreak",
|
|
"rv32ui-p-sll")
|
|
case _ => throw new CDEMatchError
|
|
}
|
|
)
|
|
|
|
class FPGAConfig extends Config (
|
|
(pname,site,here) => pname match {
|
|
case NAcquireTransactors => 4
|
|
case ExportGroundTestStatus => true
|
|
case _ => throw new CDEMatchError
|
|
}
|
|
)
|
|
|
|
class WithBlockingL1 extends Config (
|
|
knobValues = {
|
|
case "L1D_MSHRS" => 0
|
|
case _ => throw new CDEMatchError
|
|
}
|
|
)
|
|
|
|
class WithAHB extends Config(
|
|
(pname, site, here) => pname match {
|
|
case TMemoryChannels => BusType.AHB
|
|
case NExtMMIOAHBChannels => 1
|
|
})
|
|
|
|
class WithTL extends Config(
|
|
(pname, site, here) => pname match {
|
|
case TMemoryChannels => BusType.TL
|
|
case NExtMMIOTLChannels => 1
|
|
})
|
|
|
|
class DefaultFPGAConfig extends Config(new FPGAConfig ++ new BaseConfig)
|
|
|
|
class WithSmallCores extends Config (
|
|
topDefinitions = { (pname,site,here) => pname match {
|
|
case UseFPU => false
|
|
case MulUnroll => 1
|
|
case DivEarlyOut => false
|
|
case NTLBEntries => 4
|
|
case BtbKey => BtbParameters(nEntries = 0)
|
|
case StoreDataQueueDepth => 2
|
|
case ReplayQueueDepth => 2
|
|
case NAcquireTransactors => 2
|
|
case _ => throw new CDEMatchError
|
|
}},
|
|
knobValues = {
|
|
case "L1D_SETS" => 64
|
|
case "L1D_WAYS" => 1
|
|
case "L1I_SETS" => 64
|
|
case "L1I_WAYS" => 1
|
|
case "L1D_MSHRS" => 0
|
|
case _ => throw new CDEMatchError
|
|
}
|
|
)
|
|
|
|
class DefaultFPGASmallConfig extends Config(new WithSmallCores ++ new DefaultFPGAConfig)
|
|
class DefaultSmallConfig extends Config(new WithSmallCores ++ new BaseConfig)
|
|
class DefaultRV32Config extends Config(new WithRV32 ++ new DefaultSmallConfig)
|
|
|
|
class DualBankConfig extends Config(
|
|
new WithNBanksPerMemChannel(2) ++ new BaseConfig)
|
|
class DualBankL2Config extends Config(
|
|
new WithNBanksPerMemChannel(2) ++ new WithL2Cache ++ new BaseConfig)
|
|
|
|
class DualChannelConfig extends Config(new WithNMemoryChannels(2) ++ new BaseConfig)
|
|
class DualChannelL2Config extends Config(
|
|
new WithNMemoryChannels(2) ++ new WithL2Cache ++ new BaseConfig)
|
|
|
|
class DualChannelDualBankConfig extends Config(
|
|
new WithNMemoryChannels(2) ++
|
|
new WithNBanksPerMemChannel(2) ++ new BaseConfig)
|
|
class DualChannelDualBankL2Config extends Config(
|
|
new WithNMemoryChannels(2) ++ new WithNBanksPerMemChannel(2) ++
|
|
new WithL2Cache ++ new BaseConfig)
|
|
|
|
class WithRoccExample extends Config(
|
|
(pname, site, here) => pname match {
|
|
case BuildRoCC => Seq(
|
|
RoccParameters(
|
|
opcodes = OpcodeSet.custom0,
|
|
generator = (p: Parameters) => Module(new AccumulatorExample()(p))),
|
|
RoccParameters(
|
|
opcodes = OpcodeSet.custom1,
|
|
generator = (p: Parameters) => Module(new TranslatorExample()(p)),
|
|
nPTWPorts = 1),
|
|
RoccParameters(
|
|
opcodes = OpcodeSet.custom2,
|
|
generator = (p: Parameters) => Module(new CharacterCountExample()(p))))
|
|
|
|
case RoccMaxTaggedMemXacts => 1
|
|
case _ => throw new CDEMatchError
|
|
})
|
|
|
|
class RoccExampleConfig extends Config(new WithRoccExample ++ new BaseConfig)
|
|
|
|
class WithMIFDataBits(n: Int) extends Config(
|
|
(pname, site, here) => pname match {
|
|
case MIFDataBits => Dump("MIF_DATA_BITS", n)
|
|
})
|
|
|
|
class MIF128BitConfig extends Config(
|
|
new WithMIFDataBits(128) ++ new BaseConfig)
|
|
class MIF32BitConfig extends Config(
|
|
new WithMIFDataBits(32) ++ new BaseConfig)
|
|
|
|
class SmallL2Config extends Config(
|
|
new WithNMemoryChannels(2) ++ new WithNBanksPerMemChannel(4) ++
|
|
new WithL2Capacity(256) ++ new DefaultL2Config)
|
|
|
|
class SingleChannelBenchmarkConfig extends Config(new WithL2Capacity(256) ++ new DefaultL2Config)
|
|
class DualChannelBenchmarkConfig extends Config(new WithNMemoryChannels(2) ++ new SingleChannelBenchmarkConfig)
|
|
class QuadChannelBenchmarkConfig extends Config(new WithNMemoryChannels(4) ++ new SingleChannelBenchmarkConfig)
|
|
class OctoChannelBenchmarkConfig extends Config(new WithNMemoryChannels(8) ++ new SingleChannelBenchmarkConfig)
|
|
|
|
class EightChannelConfig extends Config(new WithNMemoryChannels(8) ++ new BaseConfig)
|
|
|
|
class WithSplitL2Metadata extends Config(knobValues = { case "L2_SPLIT_METADATA" => true; case _ => throw new CDEMatchError })
|
|
class SplitL2MetadataTestConfig extends Config(new WithSplitL2Metadata ++ new DefaultL2Config)
|
|
|
|
class DualCoreConfig extends Config(
|
|
new WithNCores(2) ++ new WithL2Cache ++ new BaseConfig)
|
|
|
|
class TinyConfig extends Config(
|
|
new WithRV32 ++ new WithSmallCores ++
|
|
new WithStatelessBridge ++ new BaseConfig)
|
|
|
|
class WithTestRAM extends Config(
|
|
(pname, site, here) => pname match {
|
|
case ExtraDevices => {
|
|
class TestRAMDevice extends Device {
|
|
val ramSize = 0x1000
|
|
def builder(port: ClientUncachedTileLinkIO, extra: Bundle, p: Parameters) {
|
|
val testram = Module(new TileLinkTestRAM(ramSize)(p))
|
|
testram.io <> port
|
|
}
|
|
def addrMapEntry = AddrMapEntry("testram", MemSize(ramSize, MemAttr(AddrMapProt.RW)))
|
|
}
|
|
Seq(new TestRAMDevice)
|
|
}
|
|
})
|