From dd1fed41b66f12924b88cbe33e1798740ac77a99 Mon Sep 17 00:00:00 2001 From: Howard Mao Date: Fri, 5 Aug 2016 11:07:42 -0700 Subject: [PATCH] generate BootROM contents from assembly code --- Makefrag | 2 ++ bootrom/.gitignore | 1 + bootrom/Makefile | 12 ++++++++++++ bootrom/bootrom.S | 13 +++++++++++++ bootrom/bootrom.img | Bin 0 -> 32 bytes bootrom/linker.ld | 5 +++++ emulator/Makefrag-verilator | 4 ++-- src/main/scala/Configs.scala | 1 + src/main/scala/RocketChip.scala | 23 ++++++++++------------- src/main/scala/Testing.scala | 5 ++--- vsim/Makefrag-verilog | 2 +- 11 files changed, 49 insertions(+), 19 deletions(-) create mode 100644 bootrom/.gitignore create mode 100644 bootrom/Makefile create mode 100644 bootrom/bootrom.S create mode 100755 bootrom/bootrom.img create mode 100644 bootrom/linker.ld diff --git a/Makefrag b/Makefrag index 4e1cef5a..49cd2802 100644 --- a/Makefrag +++ b/Makefrag @@ -39,6 +39,8 @@ endif timeout_cycles = 100000000 +bootrom_img = $(base_dir)/bootrom/bootrom.img + #-------------------------------------------------------------------- # DRAMSim2 #-------------------------------------------------------------------- diff --git a/bootrom/.gitignore b/bootrom/.gitignore new file mode 100644 index 00000000..50992530 --- /dev/null +++ b/bootrom/.gitignore @@ -0,0 +1 @@ +*.elf diff --git a/bootrom/Makefile b/bootrom/Makefile new file mode 100644 index 00000000..3ea5f831 --- /dev/null +++ b/bootrom/Makefile @@ -0,0 +1,12 @@ +bootrom_img = bootrom.img + +GCC=riscv64-unknown-elf-gcc +OBJCOPY=riscv64-unknown-elf-objcopy + +all: $(bootrom_img) + +%.img: %.elf + $(OBJCOPY) -O binary --change-addresses=-0x1000 --only-section .text $< $@ + +%.elf: %.S linker.ld + $(GCC) -Tlinker.ld $< -nostdlib -static -o $@ diff --git a/bootrom/bootrom.S b/bootrom/bootrom.S new file mode 100644 index 00000000..b35ee02a --- /dev/null +++ b/bootrom/bootrom.S @@ -0,0 +1,13 @@ +.text +.global _start +_start: + // This boot ROM doesn't know about any boot devices, so it just spins, + // waiting for the debugger to load a program and change the PC. + j _start // reset vector + .word 0 // reserved + .word 0 // reserved + .word 0 // pointer to config string + .word 0 // default trap vector + .word 0 + .word 0 + .word 0 diff --git a/bootrom/bootrom.img b/bootrom/bootrom.img new file mode 100755 index 0000000000000000000000000000000000000000..6d852f38bd3cd969a84d637805f29967f4d35926 GIT binary patch literal 32 Kcmd02zz+Zp003|R literal 0 HcmV?d00001 diff --git a/bootrom/linker.ld b/bootrom/linker.ld new file mode 100644 index 00000000..1b6ff96d --- /dev/null +++ b/bootrom/linker.ld @@ -0,0 +1,5 @@ +SECTIONS +{ + . = 0x1000; + .text : { *(.text) } +} diff --git a/emulator/Makefrag-verilator b/emulator/Makefrag-verilator index 051ffb30..c316fa14 100644 --- a/emulator/Makefrag-verilator +++ b/emulator/Makefrag-verilator @@ -9,12 +9,12 @@ verilog_debug = $(generated_dir_debug)/$(MODEL).$(CONFIG).v .SECONDARY: $(firrtl) $(firrtl_debug) $(verilog) $(verilog_debug) -$(generated_dir)/%.$(CONFIG).fir $(generated_dir)/%.$(CONFIG).prm $(generated_dir)/%.$(CONFIG).d: $(chisel_srcs) +$(generated_dir)/%.$(CONFIG).fir $(generated_dir)/%.$(CONFIG).prm $(generated_dir)/%.$(CONFIG).d: $(chisel_srcs) $(bootrom_img) mkdir -p $(dir $@) cd $(base_dir) && $(SBT) "run $(PROJECT) $(MODEL) $(CONFIG) --targetDir $(generated_dir)" mv $(generated_dir)/$(MODEL).fir $(generated_dir)/$(MODEL).$(CONFIG).fir -$(generated_dir_debug)/%.$(CONFIG).fir $(generated_dir_debug)/%.$(CONFIG).prm $(generated_dir_debug)/%.$(CONFIG).d: $(chisel_srcs) +$(generated_dir_debug)/%.$(CONFIG).fir $(generated_dir_debug)/%.$(CONFIG).prm $(generated_dir_debug)/%.$(CONFIG).d: $(chisel_srcs) $(bootrom_img) mkdir -p $(dir $@) cd $(base_dir) && $(SBT) "run $(PROJECT) $(MODEL) $(CONFIG) --targetDir $(generated_dir_debug)" mv $(generated_dir_debug)/$(MODEL).fir $(generated_dir_debug)/$(MODEL).$(CONFIG).fir diff --git a/src/main/scala/Configs.scala b/src/main/scala/Configs.scala index b2c7befa..5da49d2b 100644 --- a/src/main/scala/Configs.scala +++ b/src/main/scala/Configs.scala @@ -315,6 +315,7 @@ class BaseConfig extends Config ( dataBeats = innerDataBeats, dataBits = site(CacheBlockBytes) * 8) } + case BootROMFile => "./bootrom/bootrom.img" case TLKey("MMIO_Outermost") => site(TLKey("L2toMMIO")).copy(dataBeats = site(MIFDataBeats)) case NTiles => Knob("NTILES") case AsyncMemChannels => false diff --git a/src/main/scala/RocketChip.scala b/src/main/scala/RocketChip.scala index 97dac890..374be473 100644 --- a/src/main/scala/RocketChip.scala +++ b/src/main/scala/RocketChip.scala @@ -13,6 +13,8 @@ import uncore.util._ import uncore.converters._ import rocket._ import rocket.Util._ +import java.nio.{ByteBuffer,ByteOrder} +import java.nio.file.{Files, Paths} /** Top-level parameters of RocketChip, values set in e.g. PublicConfigs.scala */ @@ -56,6 +58,7 @@ case object PLICKey extends Field[PLICConfig] /** Number of clock cycles per RTC tick */ case object RTCPeriod extends Field[Int] case object AsyncDebugBus extends Field[Boolean] +case object BootROMFile extends Field[String] /** Utility trait for quick access to some relevant parameters */ trait HasTopLevelParameters { @@ -271,25 +274,19 @@ class Uncore(implicit val p: Parameters) extends Module } def makeBootROM()(implicit p: Parameters) = { - val rom = java.nio.ByteBuffer.allocate(32) - rom.order(java.nio.ByteOrder.LITTLE_ENDIAN) + val romdata = Files.readAllBytes(Paths.get(p(BootROMFile))) + val rom = ByteBuffer.wrap(romdata) + + rom.order(ByteOrder.LITTLE_ENDIAN) // for now, have the reset vector jump straight to memory val resetToMemDist = p(GlobalAddrMap)("mem").start - p(ResetVector) require(resetToMemDist == (resetToMemDist.toInt >> 12 << 12)) val configStringAddr = p(ResetVector).toInt + rom.capacity - // This boot ROM doesn't know about any boot devices, so it just spins, - // waiting for the debugger to load a program and change the PC. - rom.putInt(0x0000006f) // loop forever - rom.putInt(0) // reserved - rom.putInt(0) // reserved - rom.putInt(configStringAddr) // pointer to config string - rom.putInt(0) // default trap vector - rom.putInt(0) // ... - rom.putInt(0) // ... - rom.putInt(0) // ... - + require(rom.getInt(12) == 0, + "Config string address position should not be occupied by code") + rom.putInt(12, configStringAddr) rom.array() ++ p(ConfigString).toSeq } diff --git a/src/main/scala/Testing.scala b/src/main/scala/Testing.scala index 2c017780..04158cb3 100644 --- a/src/main/scala/Testing.scala +++ b/src/main/scala/Testing.scala @@ -4,7 +4,7 @@ package rocketchip import Chisel._ import scala.collection.mutable.{LinkedHashSet,LinkedHashMap} -import cde.{Parameters, ParameterDump, Config, Field} +import cde.{Parameters, ParameterDump, Config, Field, CDEMatchError} case object RegressionTestNames extends Field[LinkedHashSet[String]] @@ -203,8 +203,7 @@ object TestGenerator extends App { } currentConfig ++ finalConfig } - - val world = (new Config(finalConfig)).toInstance + val world = finalConfig.toInstance val paramsFromConfig: Parameters = Parameters.root(world) diff --git a/vsim/Makefrag-verilog b/vsim/Makefrag-verilog index bb91682a..3e01366e 100644 --- a/vsim/Makefrag-verilog +++ b/vsim/Makefrag-verilog @@ -16,7 +16,7 @@ else # files. .SECONDARY: $(generated_dir)/$(MODEL).$(CONFIG).fir -$(generated_dir)/%.$(CONFIG).fir $(generated_dir)/%.$(CONFIG).d $(generated_dir)/%.prm: $(chisel_srcs) +$(generated_dir)/%.$(CONFIG).fir $(generated_dir)/%.$(CONFIG).d $(generated_dir)/%.prm: $(chisel_srcs) $(bootrom_img) mkdir -p $(dir $@) cd $(base_dir) && $(SBT) "run $(PROJECT) $(notdir $*) $(CONFIG) $(CHISEL_ARGS) --configDump --noInlineMem" mv $(generated_dir)/$(MODEL).fir $(generated_dir)/$(MODEL).$(CONFIG).fir