riscv/rocket-chip
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more != wire deprecations

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This commit is contained in:
Henry Cook 2018-03-08 12:36:51 -08:00
parent 32592377c6
commit d6e2c1a73f
2 changed files with 2 additions and 2 deletions
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2
src/main/scala/devices/debug/DebugTransport.scala
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@ -172,7 +172,7 @@ class DebugTransportModuleJTAG(debugAddrBits: Int, c: JtagDTMConfig)
// But there is actually no case in the current design where you SHOULD get an error, // But there is actually no case in the current design where you SHOULD get an error,
// as we haven't implemented Bus Masters or Serial Ports, which are the only cases errors // as we haven't implemented Bus Masters or Serial Ports, which are the only cases errors
// can occur. // can occur.
nonzeroResp := stickyNonzeroRespReg | (io.dmi.resp.valid & (io.dmi.resp.bits.resp != UInt(0))) nonzeroResp := stickyNonzeroRespReg | (io.dmi.resp.valid & (io.dmi.resp.bits.resp =/= UInt(0)))
assert(!nonzeroResp, "There is no reason to get a non zero response in the current system."); assert(!nonzeroResp, "There is no reason to get a non zero response in the current system.");
assert(!stickyNonzeroRespReg, "There is no reason to have a sticky non zero response in the current system."); assert(!stickyNonzeroRespReg, "There is no reason to have a sticky non zero response in the current system.");

2
src/main/scala/devices/tilelink/BusBypass.scala
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@ -103,7 +103,7 @@ class TLBusBypassBar(implicit p: Parameters) extends LazyModule
flight := next_flight flight := next_flight
when (next_flight === UInt(0)) { bypass := io.bypass } when (next_flight === UInt(0)) { bypass := io.bypass }
val stall = (bypass != io.bypass) && a_first val stall = (bypass =/= io.bypass) && a_first
out0.a.valid := !stall && in.a.valid && bypass out0.a.valid := !stall && in.a.valid && bypass
out1.a.valid := !stall && in.a.valid && !bypass out1.a.valid := !stall && in.a.valid && !bypass