From d6e2c1a73fd41e0337dca147915256103483ff39 Mon Sep 17 00:00:00 2001 From: Henry Cook Date: Thu, 8 Mar 2018 12:36:51 -0800 Subject: [PATCH] more != wire deprecations --- src/main/scala/devices/debug/DebugTransport.scala | 2 +- src/main/scala/devices/tilelink/BusBypass.scala | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/src/main/scala/devices/debug/DebugTransport.scala b/src/main/scala/devices/debug/DebugTransport.scala index e7e2363e..8a5fd888 100644 --- a/src/main/scala/devices/debug/DebugTransport.scala +++ b/src/main/scala/devices/debug/DebugTransport.scala @@ -172,7 +172,7 @@ class DebugTransportModuleJTAG(debugAddrBits: Int, c: JtagDTMConfig) // But there is actually no case in the current design where you SHOULD get an error, // as we haven't implemented Bus Masters or Serial Ports, which are the only cases errors // can occur. - nonzeroResp := stickyNonzeroRespReg | (io.dmi.resp.valid & (io.dmi.resp.bits.resp != UInt(0))) + nonzeroResp := stickyNonzeroRespReg | (io.dmi.resp.valid & (io.dmi.resp.bits.resp =/= UInt(0))) assert(!nonzeroResp, "There is no reason to get a non zero response in the current system."); assert(!stickyNonzeroRespReg, "There is no reason to have a sticky non zero response in the current system."); diff --git a/src/main/scala/devices/tilelink/BusBypass.scala b/src/main/scala/devices/tilelink/BusBypass.scala index 9668fb89..58884cfd 100644 --- a/src/main/scala/devices/tilelink/BusBypass.scala +++ b/src/main/scala/devices/tilelink/BusBypass.scala @@ -103,7 +103,7 @@ class TLBusBypassBar(implicit p: Parameters) extends LazyModule flight := next_flight when (next_flight === UInt(0)) { bypass := io.bypass } - val stall = (bypass != io.bypass) && a_first + val stall = (bypass =/= io.bypass) && a_first out0.a.valid := !stall && in.a.valid && bypass out1.a.valid := !stall && in.a.valid && !bypass