264 lines
8.6 KiB
Scala
264 lines
8.6 KiB
Scala
// See LICENSE.SiFive for license details.
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package freechips.rocketchip.devices.debug
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import Chisel._
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import freechips.rocketchip.config._
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import freechips.rocketchip.jtag._
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import freechips.rocketchip.util._
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case class JtagDTMConfig (
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idcodeVersion : Int, // chosen by manuf.
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idcodePartNum : Int, // Chosen by manuf.
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idcodeManufId : Int, // Assigned by JEDEC
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// Note: the actual manufId is passed in through a wire.
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// Do not forget to wire up io.jtag_mfr_id through your top-level to set the
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// mfr_id for this core.
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// If you wish to use this field in the config, you can obtain it along
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// the lines of p(JtagDTMKey).idcodeManufId.U(11.W).
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debugIdleCycles : Int)
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case object JtagDTMKey extends Field[JtagDTMConfig](new JtagDTMKeyDefault())
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class JtagDTMKeyDefault extends JtagDTMConfig(
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idcodeVersion = 0,
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idcodePartNum = 0,
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idcodeManufId = 0,
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debugIdleCycles = 5) // Reasonable guess for synchronization.
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object dtmJTAGAddrs {
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def IDCODE = 0x1
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def DTM_INFO = 0x10
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def DMI_ACCESS = 0x11
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}
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class DMIAccessUpdate(addrBits: Int) extends Bundle {
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val addr = UInt(width = addrBits)
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val data = UInt(width = DMIConsts.dmiDataSize)
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val op = UInt(width = DMIConsts.dmiOpSize)
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override def cloneType = new DMIAccessUpdate(addrBits).asInstanceOf[this.type]
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}
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class DMIAccessCapture(addrBits: Int) extends Bundle {
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val addr = UInt(width = addrBits)
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val data = UInt(width = DMIConsts.dmiDataSize)
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val resp = UInt(width = DMIConsts.dmiRespSize)
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override def cloneType = new DMIAccessCapture(addrBits).asInstanceOf[this.type]
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}
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class DTMInfo extends Bundle {
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val reserved1 = UInt(15.W)
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val dmireset = Bool()
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val reserved0 = UInt(1.W)
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val dmiIdleCycles = UInt(3.W)
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val dmiStatus = UInt(2.W)
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val debugAddrBits = UInt(6.W)
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val debugVersion = UInt(4.W)
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}
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/** A wrapper around JTAG providing a reset signal and manufacturer id. */
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class SystemJTAGIO extends Bundle {
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val jtag = new JTAGIO(hasTRSTn = false).flip
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val reset = Bool(INPUT)
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val mfr_id = UInt(INPUT, 11)
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}
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class DebugTransportModuleJTAG(debugAddrBits: Int, c: JtagDTMConfig)
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(implicit val p: Parameters) extends Module {
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val io = new Bundle {
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val dmi = new DMIIO()(p)
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val jtag = Flipped(new JTAGIO(hasTRSTn = false)) // TODO: re-use SystemJTAGIO here?
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val jtag_reset = Bool(INPUT)
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val jtag_mfr_id = UInt(INPUT, 11)
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val fsmReset = Bool(OUTPUT)
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}
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//--------------------------------------------------------
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// Reg and Wire Declarations
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val dtmInfo = Wire(new DTMInfo)
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val busyReg = RegInit(Bool(false))
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val stickyBusyReg = RegInit(Bool(false))
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val stickyNonzeroRespReg = RegInit(Bool(false))
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val skipOpReg = Reg(init = Bool(false)) // Skip op because we're busy
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val downgradeOpReg = Reg(init = Bool(false)) // downgrade op because prev. failed.
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val busy = Wire(Bool())
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val nonzeroResp = Wire(Bool())
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val busyResp = Wire(new DMIAccessCapture(debugAddrBits))
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val nonbusyResp = Wire(new DMIAccessCapture(debugAddrBits))
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val dmiResp = Wire(new DMIAccessCapture(debugAddrBits))
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val nopResp = Wire(new DMIAccessCapture(debugAddrBits))
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val dmiReqReg = Reg(new DMIReq(debugAddrBits))
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val dmiReqValidReg = Reg(init = Bool(false));
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val dmiStatus = Wire(UInt(width = 2))
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//--------------------------------------------------------
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// DTM Info Chain Declaration
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dmiStatus := Cat(stickyNonzeroRespReg, stickyNonzeroRespReg | stickyBusyReg)
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dtmInfo.debugVersion := 1.U // This implements version 1 of the spec.
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dtmInfo.debugAddrBits := UInt(debugAddrBits)
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dtmInfo.dmiStatus := dmiStatus
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dtmInfo.dmiIdleCycles := UInt(c.debugIdleCycles)
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dtmInfo.reserved0 := 0.U
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dtmInfo.dmireset := false.B // This is write-only
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dtmInfo.reserved1 := 0.U
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val dtmInfoChain = Module (CaptureUpdateChain(gen = new DTMInfo()))
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dtmInfoChain.io.capture.bits := dtmInfo
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//--------------------------------------------------------
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// Debug Access Chain Declaration
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val dmiAccessChain = Module(CaptureUpdateChain(genCapture = new DMIAccessCapture(debugAddrBits),
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genUpdate = new DMIAccessUpdate(debugAddrBits)))
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//--------------------------------------------------------
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// Debug Access Support
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// Busy Register. We become busy when we first try to send a request.
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// We stop being busy when we accept a response.
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when (io.dmi.req.valid) {
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busyReg := Bool(true)
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}
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when (io.dmi.resp.fire()) {
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busyReg := Bool(false)
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}
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// We are busy during a given CAPTURE
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// if we haven't received a valid response yet or if we
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// were busy last time without a reset.
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// busyReg will still be set when we check it,
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// so the logic for checking busy looks ahead.
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busy := (busyReg & !io.dmi.resp.valid) | stickyBusyReg;
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// Downgrade/Skip. We make the decision to downgrade or skip
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// during every CAPTURE_DR, and use the result in UPDATE_DR.
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// The sticky versions are reset by write to dmiReset in DTM_INFO.
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when (dmiAccessChain.io.update.valid) {
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skipOpReg := Bool(false)
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downgradeOpReg := Bool(false)
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}
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when (dmiAccessChain.io.capture.capture) {
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skipOpReg := busy
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downgradeOpReg := (!busy & nonzeroResp)
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stickyBusyReg := busy
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stickyNonzeroRespReg := nonzeroResp
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}
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when (dtmInfoChain.io.update.valid) {
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when (dtmInfoChain.io.update.bits.dmireset) {
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stickyNonzeroRespReg := Bool(false)
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stickyBusyReg := Bool(false)
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}
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}
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// Especially for the first request, we must consider dtmResp.valid,
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// so that we don't consider junk in the FIFO to be an error response.
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// The current specification says that any non-zero response is an error.
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// But there is actually no case in the current design where you SHOULD get an error,
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// as we haven't implemented Bus Masters or Serial Ports, which are the only cases errors
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// can occur.
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nonzeroResp := stickyNonzeroRespReg | (io.dmi.resp.valid & (io.dmi.resp.bits.resp =/= UInt(0)))
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assert(!nonzeroResp, "There is no reason to get a non zero response in the current system.");
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assert(!stickyNonzeroRespReg, "There is no reason to have a sticky non zero response in the current system.");
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busyResp.addr := UInt(0)
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busyResp.resp := Fill(DMIConsts.dmiRespSize, 1.U) // Generalizing busy to 'all-F'
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busyResp.data := UInt(0)
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dmiResp.addr := dmiReqReg.addr
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dmiResp.resp := io.dmi.resp.bits.resp
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dmiResp.data := io.dmi.resp.bits.data
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nopResp.addr := UInt(0)
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nopResp.resp := UInt(0)
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nopResp.data := UInt(0)
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//--------------------------------------------------------
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// Debug Access Chain Implementation
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dmiAccessChain.io.capture.bits := Mux(busy, busyResp, Mux(io.dmi.resp.valid, dmiResp, nopResp))
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when (dmiAccessChain.io.update.valid) {
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skipOpReg := Bool(false)
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downgradeOpReg := Bool(false)
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}
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when (dmiAccessChain.io.capture.capture) {
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skipOpReg := busy
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downgradeOpReg := (!busy & nonzeroResp)
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stickyBusyReg := busy
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stickyNonzeroRespReg := nonzeroResp
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}
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//--------------------------------------------------------
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// Drive Ready Valid Interface
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val dmiReqValidCheck = Wire(init = Bool(false))
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assert(!(dmiReqValidCheck && io.dmi.req.fire()), "Conflicting updates for dmiReqValidReg, should not happen.");
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when (dmiAccessChain.io.update.valid) {
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when (skipOpReg) {
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// Do Nothing
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}.elsewhen (downgradeOpReg || (dmiAccessChain.io.update.bits.op === DMIConsts.dmi_OP_NONE)) {
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//Do Nothing
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dmiReqReg.addr := UInt(0)
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dmiReqReg.data := UInt(0)
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dmiReqReg.op := UInt(0)
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}.otherwise {
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dmiReqReg := dmiAccessChain.io.update.bits
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dmiReqValidReg := Bool(true)
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dmiReqValidCheck := Bool(true)
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}
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}
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when (io.dmi.req.fire()) {
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dmiReqValidReg := Bool(false)
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}
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io.dmi.resp.ready := dmiAccessChain.io.capture.capture
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io.dmi.req.valid := dmiReqValidReg
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// This is a name-based, not type-based assignment. Do these still work?
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io.dmi.req.bits := dmiReqReg
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//--------------------------------------------------------
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// Actual JTAG TAP
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val idcode = Wire(init = new JTAGIdcodeBundle().fromBits(0.U))
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idcode.always1 := 1.U
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idcode.version := c.idcodeVersion.U
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idcode.partNumber := c.idcodePartNum.U
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idcode.mfrId := io.jtag_mfr_id
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val tapIO = JtagTapGenerator(irLength = 5,
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instructions = Map(
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dtmJTAGAddrs.DMI_ACCESS -> dmiAccessChain,
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dtmJTAGAddrs.DTM_INFO -> dtmInfoChain),
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icode = Some(dtmJTAGAddrs.IDCODE)
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)
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tapIO.idcode.get := idcode
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tapIO.jtag <> io.jtag
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tapIO.control.jtag_reset := io.jtag_reset
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//--------------------------------------------------------
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// Reset Generation (this is fed back to us by the instantiating module,
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// and is used to reset the debug registers).
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io.fsmReset := tapIO.output.reset
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}
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