From 476db6ef397311a34c020e2e08fc0b4a0c273a6d Mon Sep 17 00:00:00 2001 From: Palmer Dabbelt Date: Sat, 5 Mar 2016 18:42:45 -0800 Subject: [PATCH 1/6] Move to a newer Scala version Chisel3 needs a newer version of Scala to run correctly. --- .gitmodules | 3 --- chisel | 1 - project/build.scala | 2 +- 3 files changed, 1 insertion(+), 5 deletions(-) delete mode 160000 chisel diff --git a/.gitmodules b/.gitmodules index c6f9f713..09c8055e 100644 --- a/.gitmodules +++ b/.gitmodules @@ -10,9 +10,6 @@ [submodule "rocket"] path = rocket url = https://github.com/ucb-bar/rocket.git -[submodule "chisel"] - path = chisel - url = https://github.com/ucb-bar/chisel.git [submodule "hardfloat"] path = hardfloat url = https://github.com/ucb-bar/berkeley-hardfloat.git diff --git a/chisel b/chisel deleted file mode 160000 index 95c889ee..00000000 --- a/chisel +++ /dev/null @@ -1 +0,0 @@ -Subproject commit 95c889ee0cb9ff177e1bbfa8dc4ed09efb5364c1 diff --git a/project/build.scala b/project/build.scala index 273e97ef..85238c0f 100644 --- a/project/build.scala +++ b/project/build.scala @@ -8,7 +8,7 @@ object BuildSettings extends Build { override lazy val settings = super.settings ++ Seq( organization := "berkeley", version := "1.2", - scalaVersion := "2.11.6", + scalaVersion := "2.11.7", parallelExecution in Global := false, traceLevel := 15, scalacOptions ++= Seq("-deprecation","-unchecked"), From 4744deec281bff000d24c822f6103d9eac83cbd7 Mon Sep 17 00:00:00 2001 From: Palmer Dabbelt Date: Sat, 5 Mar 2016 17:20:25 -0800 Subject: [PATCH 2/6] Fix the SCR file for Chisel 3 --- uncore | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/uncore b/uncore index fa6be954..e311c0a7 160000 --- a/uncore +++ b/uncore @@ -1 +1 @@ -Subproject commit fa6be954e150e5a3d64e8221b6083c9feaed4268 +Subproject commit e311c0a727384827ec4d15e6a2ad98e1c06f147e From 7d5eac189b64592e03dc6c72040214228f3b2da7 Mon Sep 17 00:00:00 2001 From: Palmer Dabbelt Date: Wed, 23 Mar 2016 16:25:11 -0700 Subject: [PATCH 3/6] Bump the uncore for some Chisel3 fixes --- uncore | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/uncore b/uncore index e311c0a7..86f68452 160000 --- a/uncore +++ b/uncore @@ -1 +1 @@ -Subproject commit e311c0a727384827ec4d15e6a2ad98e1c06f147e +Subproject commit 86f6845288d2d8feaa187331acd5a04d8cb1371e From d697559754d229a7213c95c3bec95e2b2392e847 Mon Sep 17 00:00:00 2001 From: Palmer Dabbelt Date: Sat, 5 Mar 2016 21:45:42 -0800 Subject: [PATCH 4/6] Correct the polarity of the non-backup-memory HTIF This fails in FIRRTL because <> has polarity now. --- src/main/scala/RocketChip.scala | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/main/scala/RocketChip.scala b/src/main/scala/RocketChip.scala index 5abb5073..997c4f4e 100644 --- a/src/main/scala/RocketChip.scala +++ b/src/main/scala/RocketChip.scala @@ -199,7 +199,7 @@ class Uncore(implicit val p: Parameters) extends Module VLSIUtils.padOutHTIFWithDividedClock(htif.io.host, scrFile.io.scr, outmemsys.io.mem_backup, io.mem_backup_ctrl, io.host, htifW) } else { - htif.io.host.out <> io.host.out + io.host.out <> htif.io.host.out htif.io.host.in <> io.host.in } } From cddfdf09290c2aa722d8e2de1e0a748dcf815307 Mon Sep 17 00:00:00 2001 From: Palmer Dabbelt Date: Sat, 5 Mar 2016 17:19:53 -0800 Subject: [PATCH 5/6] Add CHISEL_VERSION make argument This allows users to specify if they want to build RocketChip against Chisel 2 or 3. Since Chisel 3 is now open source we can add these submodule pointers directly to avoid a fork of upstream. --- .gitmodules | 9 ++++++ Makefrag | 8 ++++- chisel2 | 1 + chisel3 | 1 + firrtl | 1 + fsim/Makefile | 2 +- project/build.scala | 2 +- regression/Makefile | 17 ++++++----- src/main/scala/Backends.scala | 55 ----------------------------------- vsim/Makefile | 2 +- vsim/Makefrag-verilog | 40 +++++++++++++++++++++---- 11 files changed, 67 insertions(+), 71 deletions(-) create mode 160000 chisel2 create mode 160000 chisel3 create mode 160000 firrtl delete mode 100644 src/main/scala/Backends.scala diff --git a/.gitmodules b/.gitmodules index 09c8055e..af688115 100644 --- a/.gitmodules +++ b/.gitmodules @@ -10,6 +10,9 @@ [submodule "rocket"] path = rocket url = https://github.com/ucb-bar/rocket.git +[submodule "chisel"] + path = chisel2 + url = https://github.com/ucb-bar/chisel.git [submodule "hardfloat"] path = hardfloat url = https://github.com/ucb-bar/berkeley-hardfloat.git @@ -31,3 +34,9 @@ [submodule "torture"] path = torture url = https://github.com/ucb-bar/riscv-torture.git +[submodule "chisel3"] + path = chisel3 + url = https://github.com/ucb-bar/chisel3.git +[submodule "firrtl"] + path = firrtl + url = https://github.com/ucb-bar/firrtl.git diff --git a/Makefrag b/Makefrag index 5b923236..33cd334e 100644 --- a/Makefrag +++ b/Makefrag @@ -8,10 +8,16 @@ PROJECT := rocketchip CXX ?= g++ CXXFLAGS := -O1 -SBT := java -Xmx2048M -Xss8M -XX:MaxPermSize=256M -jar sbt-launch.jar +CHISEL_VERSION=2 + +SBT := CHISEL_SUBMODULE="chisel$(CHISEL_VERSION)" java -Xmx2048M -Xss8M -XX:MaxPermSize=256M -jar sbt-launch.jar SHELL := /bin/bash +ifeq ($(CHISEL_VERSION),2) CHISEL_ARGS := $(PROJECT) $(MODEL) $(CONFIG) --W0W --minimumCompatibility 3.0.0 --backend $(BACKEND) --configName $(CONFIG) --compileInitializationUnoptimized --targetDir $(generated_dir) +else +CHISEL_ARGS := --W0W --minimumCompatibility 3.0.0 --backend $(BACKEND) --configName $(CONFIG) --compileInitializationUnoptimized --targetDir $(generated_dir) +endif src_path = src/main/scala default_submodules = . junctions uncore hardfloat rocket zscale groundtest context-dependent-environments diff --git a/chisel2 b/chisel2 new file mode 160000 index 00000000..95c889ee --- /dev/null +++ b/chisel2 @@ -0,0 +1 @@ +Subproject commit 95c889ee0cb9ff177e1bbfa8dc4ed09efb5364c1 diff --git a/chisel3 b/chisel3 new file mode 160000 index 00000000..e6ee1ddb --- /dev/null +++ b/chisel3 @@ -0,0 +1 @@ +Subproject commit e6ee1ddb79c219e313e530a029d8402274fbaebc diff --git a/firrtl b/firrtl new file mode 160000 index 00000000..8ae6ece9 --- /dev/null +++ b/firrtl @@ -0,0 +1 @@ +Subproject commit 8ae6ece99dfadb8d3dd25acc3549a975e3c40bbc diff --git a/fsim/Makefile b/fsim/Makefile index 8e765a34..90407690 100644 --- a/fsim/Makefile +++ b/fsim/Makefile @@ -15,7 +15,7 @@ mem_gen = $(base_dir)/fsim/fpga_mem_gen sim_dir = . output_dir = $(sim_dir)/output -BACKEND ?= fpga +BACKEND ?= v CONFIG ?= DefaultFPGAConfig TB ?= rocketTestHarness diff --git a/project/build.scala b/project/build.scala index 85238c0f..f1c263cb 100644 --- a/project/build.scala +++ b/project/build.scala @@ -15,7 +15,7 @@ object BuildSettings extends Build { libraryDependencies ++= Seq("org.scala-lang" % "scala-reflect" % scalaVersion.value) ) - lazy val chisel = project + lazy val chisel = project in file(sys.env.getOrElse("CHISEL_SUBMODULE", "chisel2")) lazy val cde = project in file("context-dependent-environments") lazy val hardfloat = project.dependsOn(chisel) lazy val junctions = project.dependsOn(chisel, cde) diff --git a/regression/Makefile b/regression/Makefile index cda2eaf1..8bdda86d 100644 --- a/regression/Makefile +++ b/regression/Makefile @@ -16,6 +16,9 @@ ifeq ($(TORTURE_CONFIG),) $(error Set TORTURE_CONFIG to the torture configuration to run) endif +# The version of Chisel to use +CHISEL_VERSION ?= 2 + # The top-level directory that contains rocket-chip TOP ?= .. @@ -67,7 +70,7 @@ fsim-asm-tests: stamps/$(CONFIG)/fsim-asm-tests.stamp fsim-bmark-tests: stamps/$(CONFIG)/fsim-bmark-tests.stamp fsim-torture: stamps/$(CONFIG)/fsim-torture-$(TORTURE_CONFIG).stamp -submodule_names = chisel context-dependent-environments dramsim2 groundtest hardfloat junctions rocket torture uncore zscale $(ROCKETCHIP_ADDONS) +submodule_names = chisel2 chisel3 context-dependent-environments dramsim2 groundtest hardfloat junctions rocket torture uncore zscale $(ROCKETCHIP_ADDONS) # Checks out all the rocket-chip submodules stamps/other-submodules.stamp: @@ -90,28 +93,28 @@ $(RISCV)/install.stamp: # Builds the various simulators stamps/$(CONFIG)/%-verilog.stamp: stamps/other-submodules.stamp $(RISCV)/install.stamp mkdir -p $(dir $@) - +flock -x $(dir $@)/chisel-lock $(MAKE) -C $(abspath $(TOP))/$(patsubst stamps/$(CONFIG)/%-verilog.stamp,%,$@) CONFIG=$(CONFIG) RISCV=$(abspath $(RISCV)) verilog - date > $@ + +flock -x $(dir $@)/chisel-lock $(MAKE) -C $(abspath $(TOP))/$(patsubst stamps/$(CONFIG)/%-verilog.stamp,%,$@) CONFIG=$(CONFIG) RISCV=$(abspath $(RISCV)) CHISEL_VERSION=$(CHISEL_VERSION) verilog + date > $@ stamps/$(CONFIG)/%-ndebug.stamp: stamps/other-submodules.stamp $(RISCV)/install.stamp mkdir -p $(dir $@) - +flock -x $(dir $@)/chisel-lock $(MAKE) -C $(abspath $(TOP))/$(patsubst stamps/$(CONFIG)/%-ndebug.stamp,%,$@) CONFIG=$(CONFIG) RISCV=$(abspath $(RISCV)) + +flock -x $(dir $@)/chisel-lock $(MAKE) -C $(abspath $(TOP))/$(patsubst stamps/$(CONFIG)/%-ndebug.stamp,%,$@) CONFIG=$(CONFIG) RISCV=$(abspath $(RISCV)) CHISEL_VERSION=$(CHISEL_VERSION) date > $@ stamps/$(CONFIG)/%-debug.stamp: stamps/other-submodules.stamp $(RISCV)/install.stamp mkdir -p $(dir $@) - +flock -x $(dir $@)/chisel-lock $(MAKE) -C $(abspath $(TOP))/$(patsubst stamps/$(CONFIG)/%-debug.stamp,%,$@) CONFIG=$(CONFIG) RISCV=$(abspath $(RISCV)) debug + +flock -x $(dir $@)/chisel-lock $(MAKE) -C $(abspath $(TOP))/$(patsubst stamps/$(CONFIG)/%-debug.stamp,%,$@) CONFIG=$(CONFIG) RISCV=$(abspath $(RISCV)) CHISEL_VERSION=$(CHISEL_VERSION) debug date > $@ # Runs tests on one of the simulators stamps/$(CONFIG)/%-asm-tests.stamp: stamps/$(CONFIG)/%-ndebug.stamp mkdir -p $(dir $@) - $(MAKE) -C $(abspath $(TOP))/$(patsubst stamps/$(CONFIG)/%-asm-tests.stamp,%,$@) CONFIG=$(CONFIG) RISCV=$(abspath $(RISCV)) run-asm-tests + $(MAKE) -C $(abspath $(TOP))/$(patsubst stamps/$(CONFIG)/%-asm-tests.stamp,%,$@) CONFIG=$(CONFIG) RISCV=$(abspath $(RISCV)) CHISEL_VERSION=$(CHISEL_VERSION) run-asm-tests date > $@ stamps/$(CONFIG)/%-bmark-tests.stamp: stamps/$(CONFIG)/%-ndebug.stamp mkdir -p $(dir $@) - $(MAKE) -C $(abspath $(TOP))/$(patsubst stamps/$(CONFIG)/%-bmark-tests.stamp,%,$@) CONFIG=$(CONFIG) RISCV=$(abspath $(RISCV)) run-bmark-tests + $(MAKE) -C $(abspath $(TOP))/$(patsubst stamps/$(CONFIG)/%-bmark-tests.stamp,%,$@) CONFIG=$(CONFIG) RISCV=$(abspath $(RISCV)) CHISEL_VERSION=$(CHISEL_VERSION) run-bmark-tests date > $@ # The torture tests run subtly differently on the different targets, so they diff --git a/src/main/scala/Backends.scala b/src/main/scala/Backends.scala deleted file mode 100644 index 348d29e5..00000000 --- a/src/main/scala/Backends.scala +++ /dev/null @@ -1,55 +0,0 @@ -// See LICENSE for license details. - -package rocketchip - -import Chisel._ -import RocketChipBackend._ -import scala.collection.mutable.HashMap - -object RocketChipBackend { - val initMap = new HashMap[Module, Bool]() -} - -class RocketChipBackend extends VerilogBackend -{ - initMap.clear() - override def emitPortDef(m: MemAccess, idx: Int) = { - val res = new StringBuilder() - for (node <- m.mem.inputs) { - if(node.name.contains("init")) - res.append(" .init(" + node.name + "),\n") - } - (if (idx == 0) res.toString else "") + super.emitPortDef(m, idx) - } - - def addMemPin(c: Module) = { - for (m <- Driver.components) { - m bfs { _ match { - case mem: Mem[_] if mem.seqRead => - connectMemPin(m, mem) - case _ => - } } - } - } - - def connectInitPin(c: Module) { - initMap(c) = c.addPin(Bool(INPUT), "init") - if (!(initMap contains c.parent)) connectInitPin(c.parent) - initMap(c) := initMap(c.parent) - } - - def connectMemPin(c: Module, mem: Mem[_]) { - if (!(initMap contains c)) connectInitPin(c) - mem.inputs += initMap(c) - } - - def addTopLevelPin(c: Module) = { - initMap(c) = c.addPin(Bool(INPUT), "init") - } - - transforms += addTopLevelPin - transforms += addMemPin -} - -class Fame1RocketChipBackend extends RocketChipBackend with Fame1Transform - diff --git a/vsim/Makefile b/vsim/Makefile index 956d1ca4..9ea52b2c 100644 --- a/vsim/Makefile +++ b/vsim/Makefile @@ -15,7 +15,7 @@ mem_gen = $(base_dir)/vsim/vlsi_mem_gen sim_dir = . output_dir = $(sim_dir)/output -BACKEND ?= rocketchip.RocketChipBackend +BACKEND ?= v CONFIG ?= DefaultVLSIConfig TB ?= rocketTestHarness diff --git a/vsim/Makefrag-verilog b/vsim/Makefrag-verilog index 39ed5472..66034bc2 100644 --- a/vsim/Makefrag-verilog +++ b/vsim/Makefrag-verilog @@ -2,23 +2,53 @@ # Verilog Generation #-------------------------------------------------------------------- -$(generated_dir)/$(MODEL).$(CONFIG).v $(generated_dir)/$(MODEL).$(CONFIG).d : $(chisel_srcs) +ifeq ($(CHISEL_VERSION),2) +$(generated_dir)/$(MODEL).$(CONFIG).v $(generated_dir)/$(MODEL).$(CONFIG).d $(generated_dir)/$(MODEL).$(CONFIG).prm : $(chisel_srcs) cd $(base_dir) && mkdir -p $(generated_dir) && $(SBT) "run $(CHISEL_ARGS) --configDump --noInlineMem" cd $(generated_dir) && \ if [ -a $(MODEL).$(CONFIG).conf ]; then \ $(mem_gen) $(generated_dir)/$(MODEL).$(CONFIG).conf >> $(generated_dir)/$(MODEL).$(CONFIG).v; \ fi -$(generated_dir)/consts.$(CONFIG).vh: $(generated_dir)/$(MODEL).$(CONFIG).v +$(generated_dir)/memdessertMemDessert.$(CONFIG).v $(generated_dir)/memdessertMemDessert.$(CONFIG).d: $(base_dir)/$(src_path)/*.scala $(base_dir)/uncore/$(src_path)/*.scala + cd $(base_dir) && mkdir -p $(generated_dir) && $(SBT) "run $(PROJECT) MemDessert $(CONFIG) --backend v --targetDir $(generated_dir) --W0W --moduleNamePrefix memdessert --configName $(CONFIG)" + +else + +FIRRTL ?= $(base_dir)/firrtl/utils/bin/firrtl + +$(FIRRTL): + $(MAKE) -C $(base_dir)/firrtl root_dir=$(base_dir)/firrtl build + +# If I don't mark these as .SECONDARY then make will delete these internal +# files. +.SECONDARY: $(generated_dir)/$(MODEL).$(CONFIG).fir +.SECONDARY: $(generated_dir)/MemDessert.$(CONFIG).fir + +$(generated_dir)/%.$(CONFIG).fir: $(chisel_srcs) + mkdir -p $(dir $@) + cd $(base_dir) && $(SBT) "run $(PROJECT) $(patsubst %.$(CONFIG).fir,%,$(notdir $@)) $(CONFIG) $(CHISEL_ARGS) --configDump --noInlineMem" + mv $(patsubst %.$(CONFIG).fir,%.fir,$@) $@ + +$(generated_dir)/%.v $(generated_dir)/%.prm: $(generated_dir)/%.fir $(FIRRTL) + mkdir -p $(dir $@) + $(FIRRTL) $(patsubst %,-i %,$(filter %.fir,$^)) -o $@ -X verilog + +$(generated_dir)/memdessertMemDessert.$(CONFIG).v: $(generated_dir)/MemDessert.$(CONFIG).v + cat $(filter %.v,$^) \ + | sed 's@MemDessert@memdessertMemDessert@g' \ + | sed 's@Queue@memdessetQueue@g' \ + > $@ + +endif + +$(generated_dir)/consts.$(CONFIG).vh: $(generated_dir)/$(MODEL).$(CONFIG).prm echo "\`ifndef CONST_VH" > $@ echo "\`define CONST_VH" >> $@ sed -r 's/\(([A-Za-z0-9_]+),([A-Za-z0-9_]+)\)/`define \1 \2/' $(patsubst %.v,%.prm,$<) >> $@ echo "\`define TBVFRAG \"$(MODEL).$(CONFIG).tb.vfrag\"" >> $@ echo "\`endif // CONST_VH" >> $@ -$(generated_dir)/memdessertMemDessert.$(CONFIG).v $(generated_dir)/memdessertMemDessert.$(CONFIG).d: $(base_dir)/$(src_path)/*.scala $(base_dir)/uncore/$(src_path)/*.scala - cd $(base_dir) && mkdir -p $(generated_dir) && $(SBT) "run $(PROJECT) MemDessert $(CONFIG) --backend v --targetDir $(generated_dir) --W0W --moduleNamePrefix memdessert --configName $(CONFIG)" - #-------------------------------------------------------------------- # Run #-------------------------------------------------------------------- From 39cf945efb1b8e0ac36fd249f1d282697eac85ae Mon Sep 17 00:00:00 2001 From: Palmer Dabbelt Date: Sat, 5 Mar 2016 19:17:44 -0800 Subject: [PATCH 6/6] Use Chisel 3 to build verilog on Travis Chisel 3 can't build the C++ emulator, so we currently can't have direct support for testing RocketChip. We can at least test to see if the Verilog builds when run through Chisel 3, which this patch does. --- .travis.yml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/.travis.yml b/.travis.yml index 1352c647..adebcf7a 100644 --- a/.travis.yml +++ b/.travis.yml @@ -63,7 +63,7 @@ before_install: - export CXX=g++-4.8 CC=gcc-4.8 script: - - make vsim-verilog -C regression CONFIG=$CONFIG TORTURE_CONFIG=default + - make vsim-verilog -C regression CONFIG=$CONFIG TORTURE_CONFIG=default CHISEL_VERSION=3 - make fsim-verilog -C regression CONFIG=$CONFIG TORTURE_CONFIG=default - make emulator-ndebug -C regression CONFIG=$CONFIG TORTURE_CONFIG=default - make emulator-asm-tests -C regression CONFIG=$CONFIG TORTURE_CONFIG=default