riscv/rocket-chip
1
0
Fork 0
Code Releases Activity

async_reset_reg: Don't randomize the register if rst is asserted anyway

Browse Source
This commit is contained in:
Megan Wachs 2017-09-20 14:47:00 -07:00
parent cbd65cd247
commit cda89fbacb
1 changed files with 3 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
vsrc/AsyncResetReg.v
View File

@ -54,7 +54,9 @@ module AsyncResetReg (
`endif `endif
`ifdef RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT
_RAND = {1{$random}}; _RAND = {1{$random}};
q = _RAND[0]; if (~rst) begin
q = _RAND[0];
end
`endif `endif
end end
`endif // `ifdef RANDOMIZE `endif // `ifdef RANDOMIZE