From cda89fbacb770a665a95fe6dd5cc12ffb173d8ee Mon Sep 17 00:00:00 2001
From: Megan Wachs <megan@sifive.com>
Date: Wed, 20 Sep 2017 14:47:00 -0700
Subject: [PATCH] async_reset_reg: Don't randomize the register if rst is
 asserted anyway

---
 vsrc/AsyncResetReg.v | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/vsrc/AsyncResetReg.v b/vsrc/AsyncResetReg.v
index 47703f6a..aee4b639 100644
--- a/vsrc/AsyncResetReg.v
+++ b/vsrc/AsyncResetReg.v
@@ -54,7 +54,9 @@ module AsyncResetReg (
 `endif
 `ifdef RANDOMIZE_REG_INIT
       _RAND = {1{$random}};
-      q = _RAND[0];
+      if (~rst) begin
+         q = _RAND[0];
+      end
 `endif
    end
 `endif //  `ifdef RANDOMIZE