riscv/rocket-chip
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merge ALU left and right shifters

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This commit is contained in:
Andrew Waterman 2012-12-12 02:22:34 -08:00
parent f5c53ce35d
commit c921fc34a9
1 changed files with 3 additions and 2 deletions
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rocket/src/main/scala/dpath_alu.scala
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@ -61,9 +61,10 @@ class ALU(implicit conf: RocketConfiguration) extends Component
val shamt = Cat(io.in2(5) & (io.dw === DW_64), io.in2(4,0)).toUFix val shamt = Cat(io.in2(5) & (io.dw === DW_64), io.in2(4,0)).toUFix
val shin_hi_32 = Mux(isSub(io.fn), Fill(32, io.in1(31)), UFix(0,32)) val shin_hi_32 = Mux(isSub(io.fn), Fill(32, io.in1(31)), UFix(0,32))
val shin_hi = Mux(io.dw === DW_64, io.in1(63,32), shin_hi_32) val shin_hi = Mux(io.dw === DW_64, io.in1(63,32), shin_hi_32)
val shin = Cat(shin_hi, io.in1(31,0)) val shin_r = Cat(shin_hi, io.in1(31,0))
val shin = Mux(io.fn === FN_SR || io.fn === FN_SRA, shin_r, Reverse(shin_r))
val shout_r = (Cat(isSub(io.fn) & shin(63), shin).toFix >> shamt)(63,0) val shout_r = (Cat(isSub(io.fn) & shin(63), shin).toFix >> shamt)(63,0)
val shout_l = (shin << shamt)(63,0) val shout_l = Reverse(shout_r)
val bitwise_logic = val bitwise_logic =
Mux(io.fn === FN_AND, io.in1 & io.in2, Mux(io.fn === FN_AND, io.in1 & io.in2,