From c921fc34a9f65e2fe10e43ff8d2f2bdcd9ead715 Mon Sep 17 00:00:00 2001 From: Andrew Waterman Date: Wed, 12 Dec 2012 02:22:34 -0800 Subject: [PATCH] merge ALU left and right shifters --- rocket/src/main/scala/dpath_alu.scala | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/rocket/src/main/scala/dpath_alu.scala b/rocket/src/main/scala/dpath_alu.scala index 96730f73..14ec1426 100644 --- a/rocket/src/main/scala/dpath_alu.scala +++ b/rocket/src/main/scala/dpath_alu.scala @@ -61,9 +61,10 @@ class ALU(implicit conf: RocketConfiguration) extends Component val shamt = Cat(io.in2(5) & (io.dw === DW_64), io.in2(4,0)).toUFix val shin_hi_32 = Mux(isSub(io.fn), Fill(32, io.in1(31)), UFix(0,32)) val shin_hi = Mux(io.dw === DW_64, io.in1(63,32), shin_hi_32) - val shin = Cat(shin_hi, io.in1(31,0)) + val shin_r = Cat(shin_hi, io.in1(31,0)) + val shin = Mux(io.fn === FN_SR || io.fn === FN_SRA, shin_r, Reverse(shin_r)) val shout_r = (Cat(isSub(io.fn) & shin(63), shin).toFix >> shamt)(63,0) - val shout_l = (shin << shamt)(63,0) + val shout_l = Reverse(shout_r) val bitwise_logic = Mux(io.fn === FN_AND, io.in1 & io.in2,