From c8fa7c43a9a3d11decdaeb02d8af5d103a54f9ef Mon Sep 17 00:00:00 2001 From: Howard Mao Date: Thu, 14 Jan 2016 13:38:00 -0800 Subject: [PATCH] fix Chisel3 deprecation warnings --- junctions/src/main/scala/hasti.scala | 8 ++++---- junctions/src/main/scala/memserdes.scala | 2 +- junctions/src/main/scala/nasti.scala | 12 ++++++------ junctions/src/main/scala/poci.scala | 4 ++-- junctions/src/main/scala/smi.scala | 2 +- junctions/src/main/scala/util.scala | 6 +++--- 6 files changed, 17 insertions(+), 17 deletions(-) diff --git a/junctions/src/main/scala/hasti.scala b/junctions/src/main/scala/hasti.scala index f68ff2f1..fb38d1db 100644 --- a/junctions/src/main/scala/hasti.scala +++ b/junctions/src/main/scala/hasti.scala @@ -79,7 +79,7 @@ class HastiSlaveIO(implicit p: Parameters) extends HastiBundle()(p) { class HastiBus(amap: Seq[UInt=>Bool])(implicit p: Parameters) extends HastiModule()(p) { val io = new Bundle { val master = new HastiMasterIO().flip - val slaves = Vec(new HastiSlaveIO, amap.size).flip + val slaves = Vec(amap.size, new HastiSlaveIO).flip } // skid buffer @@ -149,7 +149,7 @@ class HastiBus(amap: Seq[UInt=>Bool])(implicit p: Parameters) extends HastiModul class HastiSlaveMux(n: Int)(implicit p: Parameters) extends HastiModule()(p) { val io = new Bundle { - val ins = Vec(new HastiSlaveIO, n) + val ins = Vec(n, new HastiSlaveIO) val out = new HastiSlaveIO().flip } @@ -219,8 +219,8 @@ class HastiSlaveMux(n: Int)(implicit p: Parameters) extends HastiModule()(p) { class HastiXbar(nMasters: Int, addressMap: Seq[UInt=>Bool]) (implicit p: Parameters) extends HastiModule()(p) { val io = new Bundle { - val masters = Vec(new HastiMasterIO, nMasters).flip - val slaves = Vec(new HastiSlaveIO, addressMap.size).flip + val masters = Vec(nMasters, new HastiMasterIO).flip + val slaves = Vec(addressMap.size, new HastiSlaveIO).flip } val buses = List.fill(nMasters){Module(new HastiBus(addressMap))} diff --git a/junctions/src/main/scala/memserdes.scala b/junctions/src/main/scala/memserdes.scala index c8bfd7b6..52abf3c3 100644 --- a/junctions/src/main/scala/memserdes.scala +++ b/junctions/src/main/scala/memserdes.scala @@ -208,7 +208,7 @@ class MemDesser(w: Int)(implicit p: Parameters) extends Module // test rig side class MemIOArbiter(val arbN: Int)(implicit p: Parameters) extends MIFModule { val io = new Bundle { - val inner = Vec(new MemIO, arbN).flip + val inner = Vec(arbN, new MemIO).flip val outer = new MemIO } diff --git a/junctions/src/main/scala/nasti.scala b/junctions/src/main/scala/nasti.scala index 428a0837..6624b702 100644 --- a/junctions/src/main/scala/nasti.scala +++ b/junctions/src/main/scala/nasti.scala @@ -263,7 +263,7 @@ class MemIONastiIOConverter(cacheBlockOffsetBits: Int)(implicit p: Parameters) e /** Arbitrate among arbN masters requesting to a single slave */ class NastiArbiter(val arbN: Int)(implicit p: Parameters) extends NastiModule { val io = new Bundle { - val master = Vec(new NastiIO, arbN).flip + val master = Vec(arbN, new NastiIO).flip val slave = new NastiIO } @@ -388,7 +388,7 @@ class NastiRouter(nSlaves: Int, routeSel: UInt => UInt)(implicit p: Parameters) val io = new Bundle { val master = (new NastiIO).flip - val slave = Vec(new NastiIO, nSlaves) + val slave = Vec(nSlaves, new NastiIO) } val ar_route = routeSel(io.master.ar.bits.addr) @@ -456,8 +456,8 @@ class NastiRouter(nSlaves: Int, routeSel: UInt => UInt)(implicit p: Parameters) class NastiCrossbar(nMasters: Int, nSlaves: Int, routeSel: UInt => UInt) (implicit p: Parameters) extends NastiModule { val io = new Bundle { - val masters = Vec(new NastiIO, nMasters).flip - val slaves = Vec(new NastiIO, nSlaves) + val masters = Vec(nMasters, new NastiIO).flip + val slaves = Vec(nSlaves, new NastiIO) } if (nMasters == 1) { @@ -503,8 +503,8 @@ class NastiInterconnectIO(val nMasters: Int, val nSlaves: Int) (implicit p: Parameters) extends Bundle { /* This is a bit confusing. The interconnect is a slave to the masters and * a master to the slaves. Hence why the declarations seem to be backwards. */ - val masters = Vec(new NastiIO, nMasters).flip - val slaves = Vec(new NastiIO, nSlaves) + val masters = Vec(nMasters, new NastiIO).flip + val slaves = Vec(nSlaves, new NastiIO) override def cloneType = new NastiInterconnectIO(nMasters, nSlaves).asInstanceOf[this.type] } diff --git a/junctions/src/main/scala/poci.scala b/junctions/src/main/scala/poci.scala index 0ba4bb58..01993fee 100644 --- a/junctions/src/main/scala/poci.scala +++ b/junctions/src/main/scala/poci.scala @@ -54,7 +54,7 @@ class HastiToPociBridge(implicit p: Parameters) extends HastiModule()(p) { io.out.paddr := haddr_reg io.out.pwrite := hwrite_reg(0) - io.out.psel := (state != s_idle) + io.out.psel := (state =/= s_idle) io.out.penable := (state === s_access) io.out.pwdata := io.in.hwdata io.in.hrdata := io.out.prdata @@ -66,7 +66,7 @@ class PociBus(amap: Seq[UInt=>Bool]) extends Module { val io = new Bundle { val master = new PociIO().flip - val slaves = Vec(new PociIO, amap.size) + val slaves = Vec(amap.size, new PociIO) } val psels = PriorityEncoderOH( diff --git a/junctions/src/main/scala/smi.scala b/junctions/src/main/scala/smi.scala index c7e27af2..cc314644 100644 --- a/junctions/src/main/scala/smi.scala +++ b/junctions/src/main/scala/smi.scala @@ -59,7 +59,7 @@ class SmiMem(val dataWidth: Int, val memDepth: Int) extends SmiPeripheral { class SmiArbiter(val n: Int, val dataWidth: Int, val addrWidth: Int) extends Module { val io = new Bundle { - val in = Vec(new SmiIO(dataWidth, addrWidth), n).flip + val in = Vec(n, new SmiIO(dataWidth, addrWidth)).flip val out = new SmiIO(dataWidth, addrWidth) } diff --git a/junctions/src/main/scala/util.scala b/junctions/src/main/scala/util.scala index 16950cd1..d4373164 100644 --- a/junctions/src/main/scala/util.scala +++ b/junctions/src/main/scala/util.scala @@ -22,7 +22,7 @@ class HellaFlowQueue[T <: Data](val entries: Int)(data: => T) extends Module { val maybe_full = Reg(init=Bool(false)) val enq_ptr = Counter(do_enq, entries)._1 val (deq_ptr, deq_done) = Counter(do_deq, entries) - when (do_enq != do_deq) { maybe_full := do_enq } + when (do_enq =/= do_deq) { maybe_full := do_enq } val ptr_match = enq_ptr === deq_ptr val empty = ptr_match && !maybe_full @@ -30,7 +30,7 @@ class HellaFlowQueue[T <: Data](val entries: Int)(data: => T) extends Module { val atLeastTwo = full || enq_ptr - deq_ptr >= UInt(2) do_flow := empty && io.deq.ready - val ram = SeqMem(data, entries) + val ram = SeqMem(entries, data) when (do_enq) { ram.write(enq_ptr, io.enq.bits) } val ren = io.deq.ready && (atLeastTwo || !io.deq.valid && !empty) @@ -66,7 +66,7 @@ abstract class JunctionsAbstractLockingArbiter[T <: Data](typ: T, arbN: Int) extends Module { val io = new Bundle { - val in = Vec(Decoupled(typ.cloneType), arbN).flip + val in = Vec(arbN, Decoupled(typ.cloneType)).flip val out = Decoupled(typ.cloneType) }