riscv/rocket-chip
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lowercase SMI to Smi

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This commit is contained in:
Howard Mao
2016-01-11 16:18:44 -08:00
parent d0a14c6de9
commit c81745eb8e
2 changed files with 4 additions and 4 deletions
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4
uncore/src/main/scala/scr.scala
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@@ -1,7 +1,7 @@
package uncore
import Chisel._
import junctions.{SMIIO, MMIOBase}
import junctions.{SmiIO, MMIOBase}
import cde.Parameters
class SCRIO(implicit p: Parameters) extends HtifBundle()(p) {
@@ -13,7 +13,7 @@ class SCRIO(implicit p: Parameters) extends HtifBundle()(p) {
class SCRFile(implicit p: Parameters) extends HtifModule()(p) {
val io = new Bundle {
val smi = new SMIIO(scrDataBits, scrAddrBits).flip
val smi = new SmiIO(scrDataBits, scrAddrBits).flip
val scr = new SCRIO
}