From c81745eb8e7e8913bdd2b0cf34ae8ad765601b62 Mon Sep 17 00:00:00 2001 From: Howard Mao Date: Mon, 11 Jan 2016 16:18:44 -0800 Subject: [PATCH] lowercase SMI to Smi --- uncore/src/main/scala/htif.scala | 4 ++-- uncore/src/main/scala/scr.scala | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/uncore/src/main/scala/htif.scala b/uncore/src/main/scala/htif.scala index d5b1df3d..f392fffd 100644 --- a/uncore/src/main/scala/htif.scala +++ b/uncore/src/main/scala/htif.scala @@ -40,7 +40,7 @@ class HostIO(w: Int) extends Bundle { class HtifIO(implicit p: Parameters) extends HtifBundle()(p) { val reset = Bool(INPUT) val id = UInt(INPUT, log2Up(nCores)) - val csr = new SMIIO(scrDataBits, 12).flip + val csr = new SmiIO(scrDataBits, 12).flip val debug_stats_csr = Bool(OUTPUT) // wired directly to stats register // expected to be used to quickly indicate to testbench to do logging b/c in 'interesting' work @@ -51,7 +51,7 @@ class Htif(csr_RESET: Int)(implicit val p: Parameters) extends Module with HasHt val host = new HostIO(w) val cpu = Vec(new HtifIO, nCores).flip val mem = new ClientUncachedTileLinkIO - val scr = new SMIIO(scrDataBits, scrAddrBits) + val scr = new SmiIO(scrDataBits, scrAddrBits) } io.host.debug_stats_csr := io.cpu.map(_.debug_stats_csr).reduce(_||_) diff --git a/uncore/src/main/scala/scr.scala b/uncore/src/main/scala/scr.scala index 5cf099a2..b716793d 100644 --- a/uncore/src/main/scala/scr.scala +++ b/uncore/src/main/scala/scr.scala @@ -1,7 +1,7 @@ package uncore import Chisel._ -import junctions.{SMIIO, MMIOBase} +import junctions.{SmiIO, MMIOBase} import cde.Parameters class SCRIO(implicit p: Parameters) extends HtifBundle()(p) { @@ -13,7 +13,7 @@ class SCRIO(implicit p: Parameters) extends HtifBundle()(p) { class SCRFile(implicit p: Parameters) extends HtifModule()(p) { val io = new Bundle { - val smi = new SMIIO(scrDataBits, scrAddrBits).flip + val smi = new SmiIO(scrDataBits, scrAddrBits).flip val scr = new SCRIO }