riscv/rocket-chip
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Chisel3 compatibility fix

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This commit is contained in:
Andrew Waterman 2016-03-10 15:50:44 -08:00
parent 93773a4496
commit c28d115b30
1 changed files with 1 additions and 1 deletions
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2
uncore/src/main/scala/util.scala
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@ -75,7 +75,7 @@ class FlowThroughSerializer[T <: Bundle with HasTileLinkData](gen: T, n: Int) ex
val rbits = Reg{io.in.bits} val rbits = Reg{io.in.bits}
val active = Reg(init=Bool(false)) val active = Reg(init=Bool(false))
val shifter = Vec(n, Bits(width = narrowWidth)) val shifter = Wire(Vec(n, Bits(width = narrowWidth)))
(0 until n).foreach { (0 until n).foreach {
i => shifter(i) := rbits.data((i+1)*narrowWidth-1,i*narrowWidth) i => shifter(i) := rbits.data((i+1)*narrowWidth-1,i*narrowWidth)
} }