From c28d115b306e6a78870342896177ce82a85a2476 Mon Sep 17 00:00:00 2001 From: Andrew Waterman Date: Thu, 10 Mar 2016 15:50:44 -0800 Subject: [PATCH] Chisel3 compatibility fix --- uncore/src/main/scala/util.scala | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/uncore/src/main/scala/util.scala b/uncore/src/main/scala/util.scala index 121ea68f..12316458 100644 --- a/uncore/src/main/scala/util.scala +++ b/uncore/src/main/scala/util.scala @@ -75,7 +75,7 @@ class FlowThroughSerializer[T <: Bundle with HasTileLinkData](gen: T, n: Int) ex val rbits = Reg{io.in.bits} val active = Reg(init=Bool(false)) - val shifter = Vec(n, Bits(width = narrowWidth)) + val shifter = Wire(Vec(n, Bits(width = narrowWidth))) (0 until n).foreach { i => shifter(i) := rbits.data((i+1)*narrowWidth-1,i*narrowWidth) }