From bddfa4d69bc18fced48f3e10bfc899e59ba21e63 Mon Sep 17 00:00:00 2001 From: "Wesley W. Terpstra" Date: Wed, 26 Oct 2016 13:27:35 -0700 Subject: [PATCH] Debug: make address configurable --- src/main/scala/coreplex/BaseCoreplex.scala | 4 ++-- src/main/scala/uncore/devices/Debug.scala | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/src/main/scala/coreplex/BaseCoreplex.scala b/src/main/scala/coreplex/BaseCoreplex.scala index 3210ec36..b4e23b02 100644 --- a/src/main/scala/coreplex/BaseCoreplex.scala +++ b/src/main/scala/coreplex/BaseCoreplex.scala @@ -51,7 +51,7 @@ case class CoreplexConfig( abstract class BaseCoreplex(c: CoreplexConfig)(implicit val p: Parameters) extends LazyModule with HasCoreplexParameters { val debugLegacy = LazyModule(new TLLegacy()(outerMMIOParams)) - val debugModule = LazyModule(new TLDebugModule(p(XLen)/8)) + val debugModule = LazyModule(new TLDebugModule()) debugModule.node := TLHintHandler()( TLBuffer()( @@ -121,7 +121,7 @@ abstract class BaseCoreplexModule[+L <: BaseCoreplex, +B <: BaseCoreplexBundle]( // and coherence manager(s) to the other side l1tol2net.io.clients_cached <> uncoreTileIOs.map(_.cached).flatten l1tol2net.io.clients_uncached <> uncoreTileIOs.map(_.uncached).flatten ++ io.slave - l1tol2net.io.managers <> managerEndpoints.map(_.innerTL) :+ mmioManager.io.inner + l1tol2net.io.managers <> managerEndpoints.map(_.innerTL) :+ mmioManager.io.inner // legacy goes here (not mmioManager) val mem_ic = Module(new TileLinkMemoryInterconnect(nBanksPerMemChannel, c.nMemChannels)(outerMemParams)) diff --git a/src/main/scala/uncore/devices/Debug.scala b/src/main/scala/uncore/devices/Debug.scala index e5cd0af6..76641406 100644 --- a/src/main/scala/uncore/devices/Debug.scala +++ b/src/main/scala/uncore/devices/Debug.scala @@ -823,8 +823,8 @@ trait DebugModule extends Module with HasDebugModuleParameters with HasRegMap { * */ -class TLDebugModule(beatBytes: Int) (implicit p: Parameters) - extends TLRegisterRouter(0x0, beatBytes=beatBytes)( +class TLDebugModule(address: BigInt = 0)(implicit p: Parameters) + extends TLRegisterRouter(address, beatBytes=p(rocket.XLen)/8)( new TLRegBundle(p, _ ) with DebugModuleBundle)( new TLRegModule(p, _, _) with DebugModule)