From bcc631f756d7020e32fc9549ff66007bf2bb860a Mon Sep 17 00:00:00 2001 From: Howard Mao Date: Sat, 31 Oct 2015 17:43:08 -0700 Subject: [PATCH] generate word-size requests in uncached generator --- groundtest/src/main/scala/generator.scala | 49 ++++++++++++++--------- 1 file changed, 29 insertions(+), 20 deletions(-) diff --git a/groundtest/src/main/scala/generator.scala b/groundtest/src/main/scala/generator.scala index d104c22f..bc09a227 100644 --- a/groundtest/src/main/scala/generator.scala +++ b/groundtest/src/main/scala/generator.scala @@ -21,7 +21,9 @@ class UncachedTileLinkGenerator(id: Int) (implicit p: Parameters) extends TLModule()(p) with HasGeneratorParams { private val tlBlockOffset = tlBeatAddrBits + tlByteAddrBits - private val maxAddress = (p(MMIOBase) >> tlBlockOffset).toInt / 2 + private val wordBits = 64 + private val wordOffset = log2Up(wordBits / 8) + private val maxAddress = (p(MMIOBase) >> wordOffset).toInt / 2 private val totalRequests = maxAddress / nGens val io = new Bundle { @@ -32,11 +34,7 @@ class UncachedTileLinkGenerator(id: Int) val (s_start :: s_put :: s_get :: s_finished :: Nil) = Enum(Bits(), 4) val state = Reg(init = s_start) - val (acq_beat, acq_done) = Counter(io.mem.acquire.fire() && state === s_put, tlDataBeats) - val (gnt_beat, gnt_done) = Counter(io.mem.grant.fire() && state === s_get, tlDataBeats) - val (req_cnt, req_wrap) = Counter(gnt_done && state === s_get, totalRequests) - - val addr_block = Cat(req_cnt, UInt(id, log2Up(nGens))) + val (req_cnt, req_wrap) = Counter(io.mem.grant.fire() && state === s_get, totalRequests) val sending = Reg(init = Bool(false)) @@ -46,13 +44,13 @@ class UncachedTileLinkGenerator(id: Int) } when (state === s_put) { - when (acq_done) { sending := Bool(false) } + when (io.mem.acquire.fire()) { sending := Bool(false) } when (io.mem.grant.fire()) { sending := Bool(true); state := s_get } } when (state === s_get) { when (io.mem.acquire.fire()) { sending := Bool(false) } - when (gnt_done) { + when (io.mem.grant.fire()) { sending := Bool(true) state := Mux(req_wrap, s_finished, s_put) } @@ -60,28 +58,39 @@ class UncachedTileLinkGenerator(id: Int) io.finished := (state === s_finished) - val acq_addr = Cat(addr_block, acq_beat, UInt(0, tlByteAddrBits)) - val gnt_addr = Cat(addr_block, gnt_beat, UInt(0, tlByteAddrBits)) - val data_prefix = Cat(UInt(id, log2Up(nGens)), req_cnt) - val put_data = Cat(data_prefix, acq_addr) - val get_data = Cat(data_prefix, gnt_addr) + val full_addr = Cat(req_cnt, UInt(id, log2Up(nGens)), UInt(0, wordOffset)) + val addr_block = full_addr >> UInt(tlBlockOffset) + val addr_beat = full_addr(tlBlockOffset - 1, tlByteAddrBits) + val addr_byte = full_addr(tlByteAddrBits - 1, 0) - val put_acquire = PutBlock( + val data_prefix = Cat(UInt(id, log2Up(nGens)), req_cnt) + val word_data = Wire(UInt(width = wordBits)) + word_data := Cat(data_prefix, full_addr) + val beat_data = Fill(tlDataBits / wordBits, word_data) + val wshift = Cat(full_addr(tlByteAddrBits - 1, wordOffset), UInt(0, wordOffset)) + val wmask = Fill(wordBits / 8, Bits(1, 1)) << wshift + + val put_acquire = Put( client_xact_id = UInt(0), addr_block = addr_block, - addr_beat = acq_beat, - data = put_data) + addr_beat = addr_beat, + data = beat_data, + wmask = Some(wmask)) - val get_acquire = GetBlock( + val get_acquire = Get( client_xact_id = UInt(0), - addr_block = addr_block) + addr_block = addr_block, + addr_beat = addr_beat, + addr_byte = addr_byte, + operand_size = MT_D, + alloc = Bool(true)) io.mem.acquire.valid := sending io.mem.acquire.bits := Mux(state === s_put, put_acquire, get_acquire) io.mem.grant.ready := !sending - assert(!io.mem.grant.valid || state != s_get || - io.mem.grant.bits.data === get_data, + assert(!io.mem.grant.valid || state =/= s_get || + io.mem.grant.bits.data(63, 0) === word_data, s"Get received incorrect data in uncached generator ${id}") }