Merge pull request #406 from ucb-bar/incisive-fixes
More Cadence Incisive fixes
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commit
bc01f85164
@ -25,23 +25,30 @@ module TestDriver;
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void'($value$plusargs("max-cycles=%d", max_cycles));
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void'($value$plusargs("max-cycles=%d", max_cycles));
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verbose = $test$plusargs("verbose");
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verbose = $test$plusargs("verbose");
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// do not delete the line below.
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// do not delete the lines below.
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// $random function needs to be called with the seed once to affect all
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// $random function needs to be called with the seed once to affect all
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// the downstream $random functions within the Chisel-generated Verilog
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// the downstream $random functions within the Chisel-generated Verilog
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// code.
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// code.
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// $urandom is seeded via cmdline (+ntb_random_seed in VCS) but that
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// $urandom is seeded via cmdline (+ntb_random_seed in VCS) but that
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// doesn't seed $random.
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// doesn't seed $random.
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rand_value = $random($urandom);
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rand_value = $urandom;
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rand_value = $random(rand_value);
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if (verbose) begin
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if (verbose) begin
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$fdisplay(stderr, "testing $random %0x", rand_value);
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$fdisplay(stderr, "testing $random %0x", rand_value);
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end
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end
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`ifdef DEBUG
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`ifdef DEBUG
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if ($value$plusargs("vcdplusfile=%s", vcdplusfile))
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if ($value$plusargs("vcdplusfile=%s", vcdplusfile))
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begin
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begin
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`ifdef VCS
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$vcdplusfile(vcdplusfile);
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$vcdplusfile(vcdplusfile);
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$vcdpluson(0);
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$vcdpluson(0);
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$vcdplusmemon(0);
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$vcdplusmemon(0);
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`else
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$fdisplay(stderr, "Error: +vcdplusfile is VCS-only; use +vcdfile instead");
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$fatal;
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`endif
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end
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end
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if ($value$plusargs("vcdfile=%s", vcdfile))
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if ($value$plusargs("vcdfile=%s", vcdfile))
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@ -50,8 +57,12 @@ module TestDriver;
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$dumpvars(0, testHarness);
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$dumpvars(0, testHarness);
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$dumpon;
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$dumpon;
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end
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end
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`ifdef VCS
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`define VCDPLUSCLOSE $vcdplusclose; $dumpoff;
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`define VCDPLUSCLOSE $vcdplusclose; $dumpoff;
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`else
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`else
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`define VCDPLUSCLOSE $dumpoff;
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`endif
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`else
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`define VCDPLUSCLOSE
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`define VCDPLUSCLOSE
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`endif
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`endif
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end
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end
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