From 9f0fda01b33f9822d5b91b94dbc5c48b05d51f13 Mon Sep 17 00:00:00 2001
From: Scott Johnson <scottj@sifive.com>
Date: Wed, 19 Oct 2016 13:18:17 -0700
Subject: [PATCH 1/2] Fix Cadence Incisive compile warning

The SystemVerilog LRM (IEEE 1800-2012) clause 20.15.1 ($random
function) says: "The seed argument shall be an integral variable."

This fixes the following compile warning:

    rand_value = $random($urandom);
                       |
ncelab: *W,WRNOTL (/home/scottj/rocket-chip/vsrc/TestDriver.v,34|23): Argument to out parameter is not a legal lvalue.
---
 vsrc/TestDriver.v | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/vsrc/TestDriver.v b/vsrc/TestDriver.v
index 554480d2..cb98f8ac 100644
--- a/vsrc/TestDriver.v
+++ b/vsrc/TestDriver.v
@@ -25,13 +25,14 @@ module TestDriver;
     void'($value$plusargs("max-cycles=%d", max_cycles));
     verbose = $test$plusargs("verbose");
 
-    // do not delete the line below.
+    // do not delete the lines below.
     // $random function needs to be called with the seed once to affect all
     // the downstream $random functions within the Chisel-generated Verilog
     // code.
     // $urandom is seeded via cmdline (+ntb_random_seed in VCS) but that
     // doesn't seed $random.
-    rand_value = $random($urandom);
+    rand_value = $urandom;
+    rand_value = $random(rand_value);
     if (verbose) begin
       $fdisplay(stderr, "testing $random %0x", rand_value);
     end

From a919a280e8bf453c93bb388e54373853a88a03b6 Mon Sep 17 00:00:00 2001
From: Scott Johnson <scottj@sifive.com>
Date: Wed, 19 Oct 2016 13:11:18 -0700
Subject: [PATCH 2/2] Fix Cadence Incisive compile errors; VCD-Plus is a
 VCS-only format

This fixes the following compile warnings and simulation errors:

Compile-time warnings:
      $vcdplusfile(vcdplusfile);
                 |
ncelab: *W,MISSYST (/home/scottj/rocket-chip/vsrc/TestDriver.v,42|17): Unrecognized system task or function: $vcdplusfile (did not match built-in or user-defined names) [2.7.4(IEEE Std 1364-2001)].
      $vcdpluson(0);
               |
ncelab: *W,MISSYST (/home/scottj/rocket-chip/vsrc/TestDriver.v,43|15): Unrecognized system task or function: $vcdpluson (did not match built-in or user-defined names) [2.7.4(IEEE Std 1364-2001)].
      $vcdplusmemon(0);
                  |
ncelab: *W,MISSYST (/home/scottj/rocket-chip/vsrc/TestDriver.v,44|18): Unrecognized system task or function: $vcdplusmemon (did not match built-in or user-defined names) [2.7.4(IEEE Std 1364-2001)].
        `VCDPLUSCLOSE
                    |
ncelab: *W,MISSYST (/home/scottj/rocket-chip/vsrc/TestDriver.v,89|20): Unrecognized system task or function: $vcdplusclose (did not match built-in or user-defined names) [2.7.4(IEEE Std 1364-2001)].

Which then become simulation-time errors:

      $vcdplusfile(vcdplusfile);
                 |
ncsim: *E,MSSYSTF (/home/scottj/rocket-chip/vsrc/TestDriver.v,42|17): User Defined system task or function ($vcdplusfile) registered during elaboration and used within the simulation has not been registered during simulation.
      $vcdpluson(0);
               |
ncsim: *E,MSSYSTF (/home/scottj/rocket-chip/vsrc/TestDriver.v,43|15): User Defined system task or function ($vcdpluson) registered during elaboration and used within the simulation has not been registered during simulation.
      $vcdplusmemon(0);
                  |
ncsim: *E,MSSYSTF (/home/scottj/rocket-chip/vsrc/TestDriver.v,44|18): User Defined system task or function ($vcdplusmemon) registered during elaboration and used within the simulation has not been registered during simulation.
        `VCDPLUSCLOSE
                    |
ncsim: *E,MSSYSTF (/home/scottj/rocket-chip/vsrc/TestDriver.v,89|20): User Defined system task or function ($vcdplusclose) registered during elaboration and used within the simulation has not been registered during simulation.
        `VCDPLUSCLOSE
                    |
ncsim: *E,MSSYSTF (/home/scottj/rocket-chip/vsrc/TestDriver.v,97|20): User Defined system task or function ($vcdplusclose) registered during elaboration and used within the simulation has not been registered during simulation.
---
 vsrc/TestDriver.v | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/vsrc/TestDriver.v b/vsrc/TestDriver.v
index cb98f8ac..f66d3a21 100644
--- a/vsrc/TestDriver.v
+++ b/vsrc/TestDriver.v
@@ -38,11 +38,17 @@ module TestDriver;
     end
 
 `ifdef DEBUG
+
     if ($value$plusargs("vcdplusfile=%s", vcdplusfile))
     begin
+`ifdef VCS
       $vcdplusfile(vcdplusfile);
       $vcdpluson(0);
       $vcdplusmemon(0);
+`else
+      $fdisplay(stderr, "Error: +vcdplusfile is VCS-only; use +vcdfile instead");
+      $fatal;
+`endif
     end
 
     if ($value$plusargs("vcdfile=%s", vcdfile))
@@ -51,8 +57,12 @@ module TestDriver;
       $dumpvars(0, testHarness);
       $dumpon;
     end
+`ifdef VCS
 `define VCDPLUSCLOSE $vcdplusclose; $dumpoff;
 `else
+`define VCDPLUSCLOSE $dumpoff;
+`endif
+`else
 `define VCDPLUSCLOSE
 `endif
   end