RocketTile: if the dcache is incoherent, report it in DTS
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@ -66,6 +66,9 @@ class RocketTile(val rocketParams: RocketTileParams)(implicit p: Parameters) ext
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val itim = if (frontend.icache.slaveNode.edges.in.isEmpty) Map() else Map(
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val itim = if (frontend.icache.slaveNode.edges.in.isEmpty) Map() else Map(
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"sifive,itim" -> ofRef(frontend.icache.device))
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"sifive,itim" -> ofRef(frontend.icache.device))
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val incoherent = if (!rocketParams.core.useAtomicsOnlyForIO) Map() else Map(
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"sifive,d-cache-incoherent" -> Nil)
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val icache = rocketParams.icache.map(i => Map(
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val icache = rocketParams.icache.map(i => Map(
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"i-cache-block-size" -> ofInt(block),
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"i-cache-block-size" -> ofInt(block),
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"i-cache-sets" -> ofInt(i.nSets),
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"i-cache-sets" -> ofInt(i.nSets),
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@ -105,7 +108,7 @@ class RocketTile(val rocketParams: RocketTileParams)(implicit p: Parameters) ext
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"status" -> ofStr("okay"),
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"status" -> ofStr("okay"),
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"clock-frequency" -> Seq(ResourceInt(rocketParams.core.bootFreqHz)),
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"clock-frequency" -> Seq(ResourceInt(rocketParams.core.bootFreqHz)),
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"riscv,isa" -> ofStr(isa))
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"riscv,isa" -> ofStr(isa))
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++ dcache ++ icache ++ nextlevel ++ mmu ++ itlb ++ dtlb ++ dtim ++itim)
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++ dcache ++ icache ++ nextlevel ++ mmu ++ itlb ++ dtlb ++ dtim ++ itim ++ incoherent)
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}
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}
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}
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}
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val intcDevice = new Device {
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val intcDevice = new Device {
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