diff --git a/src/main/scala/tile/RocketTile.scala b/src/main/scala/tile/RocketTile.scala
index ebfcde9d..436efeea 100644
--- a/src/main/scala/tile/RocketTile.scala
+++ b/src/main/scala/tile/RocketTile.scala
@@ -66,6 +66,9 @@ class RocketTile(val rocketParams: RocketTileParams)(implicit p: Parameters) ext
       val itim = if (frontend.icache.slaveNode.edges.in.isEmpty) Map() else Map(
         "sifive,itim"          -> ofRef(frontend.icache.device))
 
+      val incoherent = if (!rocketParams.core.useAtomicsOnlyForIO) Map() else Map(
+        "sifive,d-cache-incoherent" -> Nil)
+
       val icache = rocketParams.icache.map(i => Map(
         "i-cache-block-size"   -> ofInt(block),
         "i-cache-sets"         -> ofInt(i.nSets),
@@ -105,7 +108,7 @@ class RocketTile(val rocketParams: RocketTileParams)(implicit p: Parameters) ext
         "status"               -> ofStr("okay"),
         "clock-frequency"      -> Seq(ResourceInt(rocketParams.core.bootFreqHz)),
         "riscv,isa"            -> ofStr(isa))
-        ++ dcache ++ icache ++ nextlevel ++ mmu ++ itlb ++ dtlb ++ dtim ++itim)
+        ++ dcache ++ icache ++ nextlevel ++ mmu ++ itlb ++ dtlb ++ dtim ++ itim ++ incoherent)
     }
   }
   val intcDevice = new Device {