coreplex: make rational+synchronous crossing configurable (#688)
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@ -20,7 +20,7 @@ class BaseCoreplexConfig extends Config ((site, here, up) => {
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case ASIdBits => 0
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case ASIdBits => 0
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case XLen => 64 // Applies to all cores
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case XLen => 64 // Applies to all cores
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case BuildCore => (p: Parameters) => new Rocket()(p)
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case BuildCore => (p: Parameters) => new Rocket()(p)
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case RocketCrossing => Synchronous
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case RocketCrossing => SynchronousCrossing()
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case RocketTilesKey => Nil
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case RocketTilesKey => Nil
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case DMKey => DefaultDebugModuleConfig(site(XLen))
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case DMKey => DefaultDebugModuleConfig(site(XLen))
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case NTiles => site(RocketTilesKey).size
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case NTiles => site(RocketTilesKey).size
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@ -211,13 +211,13 @@ class WithBootROMFile(bootROMFile: String) extends Config((site, here, up) => {
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})
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})
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class WithSynchronousRocketTiles extends Config((site, here, up) => {
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class WithSynchronousRocketTiles extends Config((site, here, up) => {
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case RocketCrossing => Synchronous
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case RocketCrossing => SynchronousCrossing()
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})
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})
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class WithAynchronousRocketTiles(depth: Int, sync: Int) extends Config((site, here, up) => {
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class WithAynchronousRocketTiles(depth: Int, sync: Int) extends Config((site, here, up) => {
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case RocketCrossing => Asynchronous(depth, sync)
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case RocketCrossing => AsynchronousCrossing(depth, sync)
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})
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})
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class WithRationalRocketTiles extends Config((site, here, up) => {
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class WithRationalRocketTiles extends Config((site, here, up) => {
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case RocketCrossing => Rational
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case RocketCrossing => RationalCrossing()
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})
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})
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@ -11,9 +11,9 @@ import uncore.tilelink2._
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import util._
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import util._
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sealed trait ClockCrossing
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sealed trait ClockCrossing
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case object Synchronous extends ClockCrossing
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case class SynchronousCrossing(params: BufferParams = BufferParams.default) extends ClockCrossing
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case object Rational extends ClockCrossing
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case class RationalCrossing(direction: RationalDirection = FastToSlow) extends ClockCrossing
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case class Asynchronous(depth: Int, sync: Int = 2) extends ClockCrossing
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case class AsynchronousCrossing(depth: Int, sync: Int = 2) extends ClockCrossing
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case object RocketTilesKey extends Field[Seq[RocketTileParams]]
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case object RocketTilesKey extends Field[Seq[RocketTileParams]]
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case object RocketCrossing extends Field[ClockCrossing]
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case object RocketCrossing extends Field[ClockCrossing]
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@ -47,9 +47,9 @@ trait HasRocketTiles extends CoreplexRISCVPlatform {
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lip.foreach { intBar.intnode := _ } // lip
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lip.foreach { intBar.intnode := _ } // lip
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crossing match {
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crossing match {
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case Synchronous => {
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case SynchronousCrossing(params) => {
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val wrapper = LazyModule(new SyncRocketTile(c, i)(pWithExtra))
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val wrapper = LazyModule(new SyncRocketTile(c, i)(pWithExtra))
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val buffer = LazyModule(new TLBuffer)
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val buffer = LazyModule(new TLBuffer(params))
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val fixer = LazyModule(new TLFIFOFixer)
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val fixer = LazyModule(new TLFIFOFixer)
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buffer.node :=* wrapper.masterNode
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buffer.node :=* wrapper.masterNode
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fixer.node :=* buffer.node
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fixer.node :=* buffer.node
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@ -62,7 +62,7 @@ trait HasRocketTiles extends CoreplexRISCVPlatform {
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wrapper.module.io.resetVector := io.resetVector
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wrapper.module.io.resetVector := io.resetVector
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}
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}
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}
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}
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case Asynchronous(depth, sync) => {
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case AsynchronousCrossing(depth, sync) => {
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val wrapper = LazyModule(new AsyncRocketTile(c, i)(pWithExtra))
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val wrapper = LazyModule(new AsyncRocketTile(c, i)(pWithExtra))
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val sink = LazyModule(new TLAsyncCrossingSink(depth, sync))
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val sink = LazyModule(new TLAsyncCrossingSink(depth, sync))
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val source = LazyModule(new TLAsyncCrossingSource(sync))
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val source = LazyModule(new TLAsyncCrossingSource(sync))
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@ -80,9 +80,9 @@ trait HasRocketTiles extends CoreplexRISCVPlatform {
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wrapper.module.io.resetVector := io.resetVector
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wrapper.module.io.resetVector := io.resetVector
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}
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}
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}
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}
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case Rational => {
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case RationalCrossing(direction) => {
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val wrapper = LazyModule(new RationalRocketTile(c, i)(pWithExtra))
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val wrapper = LazyModule(new RationalRocketTile(c, i)(pWithExtra))
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val sink = LazyModule(new TLRationalCrossingSink(util.FastToSlow))
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val sink = LazyModule(new TLRationalCrossingSink(direction))
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val source = LazyModule(new TLRationalCrossingSource)
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val source = LazyModule(new TLRationalCrossingSource)
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val fixer = LazyModule(new TLFIFOFixer)
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val fixer = LazyModule(new TLFIFOFixer)
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sink.node :=* wrapper.masterNode
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sink.node :=* wrapper.masterNode
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@ -114,7 +114,7 @@ class RationalCrossingSink[T <: Data](gen: T, direction: RationalDirection = Sym
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}
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}
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}
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}
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class RationalCrossing[T <: Data](gen: T, direction: RationalDirection = Symmetric) extends Module
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class RationalCrossingFull[T <: Data](gen: T, direction: RationalDirection = Symmetric) extends Module
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{
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{
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val io = new CrossingIO(gen)
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val io = new CrossingIO(gen)
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