From b4d17c76d152084c5aba676bb45252c3657c8f34 Mon Sep 17 00:00:00 2001
From: "Wesley W. Terpstra" <wesley@sifive.com>
Date: Wed, 19 Apr 2017 16:16:05 -0700
Subject: [PATCH] coreplex: make rational+synchronous crossing configurable
 (#688)

---
 src/main/scala/coreplex/Configs.scala      |  8 ++++----
 src/main/scala/coreplex/RocketTiles.scala  | 16 ++++++++--------
 src/main/scala/util/RationalCrossing.scala |  2 +-
 3 files changed, 13 insertions(+), 13 deletions(-)

diff --git a/src/main/scala/coreplex/Configs.scala b/src/main/scala/coreplex/Configs.scala
index 29a2d028..a5ccc232 100644
--- a/src/main/scala/coreplex/Configs.scala
+++ b/src/main/scala/coreplex/Configs.scala
@@ -20,7 +20,7 @@ class BaseCoreplexConfig extends Config ((site, here, up) => {
   case ASIdBits => 0
   case XLen => 64 // Applies to all cores
   case BuildCore => (p: Parameters) => new Rocket()(p)
-  case RocketCrossing => Synchronous
+  case RocketCrossing => SynchronousCrossing()
   case RocketTilesKey =>  Nil
   case DMKey => DefaultDebugModuleConfig(site(XLen))
   case NTiles => site(RocketTilesKey).size
@@ -211,13 +211,13 @@ class WithBootROMFile(bootROMFile: String) extends Config((site, here, up) => {
 })
 
 class WithSynchronousRocketTiles extends Config((site, here, up) => {
-  case RocketCrossing => Synchronous
+  case RocketCrossing => SynchronousCrossing()
 })
 
 class WithAynchronousRocketTiles(depth: Int, sync: Int) extends Config((site, here, up) => {
-  case RocketCrossing => Asynchronous(depth, sync)
+  case RocketCrossing => AsynchronousCrossing(depth, sync)
 })
 
 class WithRationalRocketTiles extends Config((site, here, up) => {
-  case RocketCrossing => Rational
+  case RocketCrossing => RationalCrossing()
 })
diff --git a/src/main/scala/coreplex/RocketTiles.scala b/src/main/scala/coreplex/RocketTiles.scala
index 3622d3da..4e531f26 100644
--- a/src/main/scala/coreplex/RocketTiles.scala
+++ b/src/main/scala/coreplex/RocketTiles.scala
@@ -11,9 +11,9 @@ import uncore.tilelink2._
 import util._
 
 sealed trait ClockCrossing
-case object Synchronous extends ClockCrossing
-case object Rational extends ClockCrossing
-case class Asynchronous(depth: Int, sync: Int = 2) extends ClockCrossing
+case class SynchronousCrossing(params: BufferParams = BufferParams.default) extends ClockCrossing
+case class RationalCrossing(direction: RationalDirection = FastToSlow) extends ClockCrossing
+case class AsynchronousCrossing(depth: Int, sync: Int = 2) extends ClockCrossing
 
 case object RocketTilesKey extends Field[Seq[RocketTileParams]]
 case object RocketCrossing extends Field[ClockCrossing]
@@ -47,9 +47,9 @@ trait HasRocketTiles extends CoreplexRISCVPlatform {
     lip.foreach { intBar.intnode := _ }              // lip
 
     crossing match {
-      case Synchronous => {
+      case SynchronousCrossing(params) => {
         val wrapper = LazyModule(new SyncRocketTile(c, i)(pWithExtra))
-        val buffer = LazyModule(new TLBuffer)
+        val buffer = LazyModule(new TLBuffer(params))
         val fixer = LazyModule(new TLFIFOFixer)
         buffer.node :=* wrapper.masterNode
         fixer.node :=* buffer.node
@@ -62,7 +62,7 @@ trait HasRocketTiles extends CoreplexRISCVPlatform {
           wrapper.module.io.resetVector := io.resetVector
         }
       }
-      case Asynchronous(depth, sync) => {
+      case AsynchronousCrossing(depth, sync) => {
         val wrapper = LazyModule(new AsyncRocketTile(c, i)(pWithExtra))
         val sink = LazyModule(new TLAsyncCrossingSink(depth, sync))
         val source = LazyModule(new TLAsyncCrossingSource(sync))
@@ -80,9 +80,9 @@ trait HasRocketTiles extends CoreplexRISCVPlatform {
           wrapper.module.io.resetVector := io.resetVector
         }
       }
-      case Rational => {
+      case RationalCrossing(direction) => {
         val wrapper = LazyModule(new RationalRocketTile(c, i)(pWithExtra))
-        val sink = LazyModule(new TLRationalCrossingSink(util.FastToSlow))
+        val sink = LazyModule(new TLRationalCrossingSink(direction))
         val source = LazyModule(new TLRationalCrossingSource)
         val fixer = LazyModule(new TLFIFOFixer)
         sink.node :=* wrapper.masterNode
diff --git a/src/main/scala/util/RationalCrossing.scala b/src/main/scala/util/RationalCrossing.scala
index 26a7673d..2c55b4f0 100644
--- a/src/main/scala/util/RationalCrossing.scala
+++ b/src/main/scala/util/RationalCrossing.scala
@@ -114,7 +114,7 @@ class RationalCrossingSink[T <: Data](gen: T, direction: RationalDirection = Sym
   }
 }
 
-class RationalCrossing[T <: Data](gen: T, direction: RationalDirection = Symmetric) extends Module
+class RationalCrossingFull[T <: Data](gen: T, direction: RationalDirection = Symmetric) extends Module
 {
   val io = new CrossingIO(gen)