riscv/rocket-chip
1
0
Fork 0
Code Releases Activity

coreplex: make rational+synchronous crossing configurable (#688)

Browse Source
This commit is contained in:
Wesley W. Terpstra
2017-04-19 16:16:05 -07:00
committed by GitHub
parent 408107447c
commit b4d17c76d1
3 changed files with 13 additions and 13 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
src/main/scala/util/RationalCrossing.scala
View File

@ -114,7 +114,7 @@ class RationalCrossingSink[T <: Data](gen: T, direction: RationalDirection = Sym
}
}
class RationalCrossing[T <: Data](gen: T, direction: RationalDirection = Symmetric) extends Module
class RationalCrossingFull[T <: Data](gen: T, direction: RationalDirection = Symmetric) extends Module
{
val io = new CrossingIO(gen)