Fix Chisel3 build for XLen=32
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@ -357,15 +357,17 @@ class CSRFile(implicit p: Parameters) extends CoreModule()(p)
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io.status.sd_rv32 := io.status.sd
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io.status.sd_rv32 := io.status.sd
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when (io.exception || csr_xcpt) {
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when (io.exception || csr_xcpt) {
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val ldst_badaddr = {
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def compressVAddr(addr: UInt) =
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val (upper, lower) = Split(io.rw.wdata, vaddrBits)
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if (vaddrBitsExtended == vaddrBits) addr
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val sign = Mux(lower.toSInt < SInt(0), upper.andR, upper.orR)
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else {
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Cat(sign, lower)
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val (upper, lower) = Split(addr, vaddrBits)
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}
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val sign = Mux(lower.toSInt < SInt(0), upper.andR, upper.orR)
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Cat(sign, lower)
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}
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val ldst =
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val ldst =
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cause === Causes.fault_load || cause === Causes.misaligned_load ||
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cause === Causes.fault_load || cause === Causes.misaligned_load ||
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cause === Causes.fault_store || cause === Causes.misaligned_store
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cause === Causes.fault_store || cause === Causes.misaligned_store
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val badaddr = Mux(ldst, ldst_badaddr, io.pc)
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val badaddr = Mux(ldst, compressVAddr(io.rw.wdata), io.pc)
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val epc = ~(~io.pc | (coreInstBytes-1))
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val epc = ~(~io.pc | (coreInstBytes-1))
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val pie = read_mstatus(reg_mstatus.prv)
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val pie = read_mstatus(reg_mstatus.prv)
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@ -14,7 +14,9 @@ object Util {
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implicit def seqToVec[T <: Data](x: Seq[T]): Vec[T] = Vec(x)
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implicit def seqToVec[T <: Data](x: Seq[T]): Vec[T] = Vec(x)
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implicit def wcToUInt(c: WideCounter): UInt = c.value
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implicit def wcToUInt(c: WideCounter): UInt = c.value
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implicit def sextToConv(x: UInt) = new AnyRef {
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implicit def sextToConv(x: UInt) = new AnyRef {
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def sextTo(n: Int): UInt = Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x)
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def sextTo(n: Int): UInt =
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if (x.getWidth == n) x
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else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x)
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}
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}
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implicit def intToUnsigned(x: Int): Unsigned = new Unsigned(x)
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implicit def intToUnsigned(x: Int): Unsigned = new Unsigned(x)
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