diff --git a/rocket/src/main/scala/csr.scala b/rocket/src/main/scala/csr.scala
index 71c139de..4186cf5e 100644
--- a/rocket/src/main/scala/csr.scala
+++ b/rocket/src/main/scala/csr.scala
@@ -357,15 +357,17 @@ class CSRFile(implicit p: Parameters) extends CoreModule()(p)
     io.status.sd_rv32 := io.status.sd
 
   when (io.exception || csr_xcpt) {
-    val ldst_badaddr = {
-      val (upper, lower) = Split(io.rw.wdata, vaddrBits)
-      val sign = Mux(lower.toSInt < SInt(0), upper.andR, upper.orR)
-      Cat(sign, lower)
-    }
+    def compressVAddr(addr: UInt) =
+      if (vaddrBitsExtended == vaddrBits) addr
+      else {
+        val (upper, lower) = Split(addr, vaddrBits)
+        val sign = Mux(lower.toSInt < SInt(0), upper.andR, upper.orR)
+        Cat(sign, lower)
+      }
     val ldst =
       cause === Causes.fault_load || cause === Causes.misaligned_load ||
       cause === Causes.fault_store || cause === Causes.misaligned_store
-    val badaddr = Mux(ldst, ldst_badaddr, io.pc)
+    val badaddr = Mux(ldst, compressVAddr(io.rw.wdata), io.pc)
     val epc = ~(~io.pc | (coreInstBytes-1))
     val pie = read_mstatus(reg_mstatus.prv)
 
diff --git a/rocket/src/main/scala/util.scala b/rocket/src/main/scala/util.scala
index a6ac1ad5..18dec13e 100644
--- a/rocket/src/main/scala/util.scala
+++ b/rocket/src/main/scala/util.scala
@@ -14,7 +14,9 @@ object Util {
   implicit def seqToVec[T <: Data](x: Seq[T]): Vec[T] = Vec(x)
   implicit def wcToUInt(c: WideCounter): UInt = c.value
   implicit def sextToConv(x: UInt) = new AnyRef {
-    def sextTo(n: Int): UInt = Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x)
+    def sextTo(n: Int): UInt =
+      if (x.getWidth == n) x
+      else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x)
   }
 
   implicit def intToUnsigned(x: Int): Unsigned = new Unsigned(x)