riscv/rocket-chip
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Fix Chisel3 build for XLen=32

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This commit is contained in:
Andrew Waterman
2016-03-30 22:48:51 -07:00
parent 70664bbca0
commit adb7eacf6e
2 changed files with 11 additions and 7 deletions
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4
rocket/src/main/scala/util.scala
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@ -14,7 +14,9 @@ object Util {
implicit def seqToVec[T <: Data](x: Seq[T]): Vec[T] = Vec(x)
implicit def wcToUInt(c: WideCounter): UInt = c.value
implicit def sextToConv(x: UInt) = new AnyRef {
def sextTo(n: Int): UInt = Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x)
def sextTo(n: Int): UInt =
if (x.getWidth == n) x
else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x)
}
implicit def intToUnsigned(x: Int): Unsigned = new Unsigned(x)