riscv/rocket-chip
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Add Wire() wrap

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This commit is contained in:
Andrew Waterman
2015-07-15 20:24:18 -07:00
parent 5b7f3c3006
commit ac6e73e317
8 changed files with 38 additions and 42 deletions
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11
rocket/src/main/scala/csr.scala
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@ -134,7 +134,7 @@ class CSRFile extends CoreModule
io.interrupt_cause := 0
io.interrupt := io.interrupt_cause(xLen-1)
val some_interrupt_pending = Bool(); some_interrupt_pending := false
val some_interrupt_pending = Wire(init=Bool(false))
def checkInterrupt(max_priv: UInt, cond: Bool, num: Int) = {
when (cond && (reg_mstatus.prv < max_priv || reg_mstatus.prv === max_priv && reg_mstatus.ie)) {
io.interrupt_cause := UInt((BigInt(1) << (xLen-1)) + num)
@ -216,20 +216,17 @@ class CSRFile extends CoreModule
CSRs.mfromhost -> reg_fromhost)
if (params(UseVM)) {
val read_sstatus = new SStatus
read_sstatus := new SStatus().fromBits(read_mstatus) // sstatus mostly overlaps mstatus
val read_sstatus = Wire(init=new SStatus().fromBits(read_mstatus))
read_sstatus.zero1 := 0
read_sstatus.zero2 := 0
read_sstatus.zero3 := 0
read_sstatus.zero4 := 0
val read_sip = new MIP
read_sip := new MIP().fromBits(0)
val read_sip = Wire(init=new MIP().fromBits(0))
read_sip.ssip := reg_mip.ssip
read_sip.stip := reg_mip.stip
val read_sie = new MIP
read_sie := new MIP().fromBits(0)
val read_sie = Wire(init=new MIP().fromBits(0))
read_sie.ssip := reg_mie.ssip
read_sie.stip := reg_mie.stip