diff --git a/rocket/src/main/scala/btb.scala b/rocket/src/main/scala/btb.scala
index 878b7e09..cb372746 100644
--- a/rocket/src/main/scala/btb.scala
+++ b/rocket/src/main/scala/btb.scala
@@ -56,7 +56,7 @@ class BHTResp extends Bundle with BTBParameters {
 class BHT(nbht: Int) {
   val nbhtbits = log2Up(nbht)
   def get(addr: UInt, update: Bool): BHTResp = {
-    val res = new BHTResp
+    val res = Wire(new BHTResp)
     val index = addr(nbhtbits+1,2) ^ history
     res.value := table(index)
     res.history := history
@@ -178,7 +178,7 @@ class BTB(updates_out_of_order: Boolean = false) extends Module with BTBParamete
 
   val useUpdatePageHit = updatePageHit.orR
   val doIdxPageRepl = !useUpdatePageHit
-  val idxPageRepl = UInt()
+  val idxPageRepl = Wire(UInt())
   val idxPageUpdateOH = Mux(useUpdatePageHit, updatePageHit, idxPageRepl)
   val idxPageUpdate = OHToUInt(idxPageUpdateOH)
   val idxPageReplEn = Mux(doIdxPageRepl, idxPageRepl, UInt(0))
diff --git a/rocket/src/main/scala/csr.scala b/rocket/src/main/scala/csr.scala
index 3483453c..ab064dad 100644
--- a/rocket/src/main/scala/csr.scala
+++ b/rocket/src/main/scala/csr.scala
@@ -134,7 +134,7 @@ class CSRFile extends CoreModule
 
   io.interrupt_cause := 0
   io.interrupt := io.interrupt_cause(xLen-1)
-  val some_interrupt_pending = Bool(); some_interrupt_pending := false
+  val some_interrupt_pending = Wire(init=Bool(false))
   def checkInterrupt(max_priv: UInt, cond: Bool, num: Int) = {
     when (cond && (reg_mstatus.prv < max_priv || reg_mstatus.prv === max_priv && reg_mstatus.ie)) {
       io.interrupt_cause := UInt((BigInt(1) << (xLen-1)) + num)
@@ -216,20 +216,17 @@ class CSRFile extends CoreModule
     CSRs.mfromhost -> reg_fromhost)
 
   if (params(UseVM)) {
-    val read_sstatus = new SStatus
-    read_sstatus := new SStatus().fromBits(read_mstatus) // sstatus mostly overlaps mstatus
+    val read_sstatus = Wire(init=new SStatus().fromBits(read_mstatus))
     read_sstatus.zero1 := 0
     read_sstatus.zero2 := 0
     read_sstatus.zero3 := 0
     read_sstatus.zero4 := 0
 
-    val read_sip = new MIP
-    read_sip := new MIP().fromBits(0)
+    val read_sip = Wire(init=new MIP().fromBits(0))
     read_sip.ssip := reg_mip.ssip
     read_sip.stip := reg_mip.stip
 
-    val read_sie = new MIP
-    read_sie := new MIP().fromBits(0)
+    val read_sie = Wire(init=new MIP().fromBits(0))
     read_sie.ssip := reg_mie.ssip
     read_sie.stip := reg_mie.stip
 
diff --git a/rocket/src/main/scala/ctrl.scala b/rocket/src/main/scala/ctrl.scala
index 991ed4b5..df580ca1 100644
--- a/rocket/src/main/scala/ctrl.scala
+++ b/rocket/src/main/scala/ctrl.scala
@@ -359,7 +359,7 @@ class Control extends CoreModule
   if (!params(BuildFPU).isEmpty && params(FDivSqrt)) decode_table ++= FDivSqrtDecode.table
   if (!params(BuildRoCC).isEmpty) decode_table ++= RoCCDecode.table
 
-  val id_ctrl = new IntCtrlSigs().decode(io.dpath.inst, decode_table)
+  val id_ctrl = Wire(new IntCtrlSigs()).decode(io.dpath.inst, decode_table)
   val ex_ctrl = Reg(new IntCtrlSigs)
   val mem_ctrl = Reg(new IntCtrlSigs)
   val wb_ctrl = Reg(new IntCtrlSigs)
@@ -389,21 +389,21 @@ class Control extends CoreModule
   val wb_reg_cause           = Reg(UInt())
   val wb_reg_rocc_pending    = Reg(init=Bool(false))
 
-  val take_pc_wb = Bool()
+  val take_pc_wb = Wire(Bool())
   val mem_misprediction = io.dpath.mem_misprediction && mem_reg_valid && (mem_ctrl.branch || mem_ctrl.jalr || mem_ctrl.jal)
   val want_take_pc_mem = mem_reg_valid && (mem_misprediction || mem_reg_flush_pipe)
   val take_pc_mem = want_take_pc_mem && !io.dpath.mem_npc_misaligned
   val take_pc_mem_wb = take_pc_wb || take_pc_mem
   val take_pc = take_pc_mem_wb
-  val ctrl_killd = Bool()
-  val ctrl_killx = Bool()
-  val ctrl_killm = Bool()
+  val ctrl_killd = Wire(Bool())
+  val ctrl_killx = Wire(Bool())
+  val ctrl_killm = Wire(Bool())
 
   val id_raddr3 = io.dpath.inst(31,27)
   val id_raddr2 = io.dpath.inst(24,20)
   val id_raddr1 = io.dpath.inst(19,15)
   val id_waddr  = io.dpath.inst(11,7)
-  val id_load_use = Bool()
+  val id_load_use = Wire(Bool())
   val id_reg_fence = Reg(init=Bool(false))
 
   val id_csr_en = id_ctrl.csr != CSR.N
diff --git a/rocket/src/main/scala/dpath.scala b/rocket/src/main/scala/dpath.scala
index 0161da34..c7caa4f7 100644
--- a/rocket/src/main/scala/dpath.scala
+++ b/rocket/src/main/scala/dpath.scala
@@ -38,7 +38,7 @@ class Datapath extends CoreModule
   val wb_reg_pc = Reg(UInt())
   val wb_reg_inst = Reg(Bits())
   val wb_reg_wdata = Reg(Bits())
-  val wb_wdata = Bits()
+  val wb_wdata = Wire(Bits())
   val wb_reg_rs2 = Reg(Bits())
 
   // instruction decode stage
@@ -51,7 +51,7 @@ class Datapath extends CoreModule
     private var canRead = true
     def read(addr: UInt) = {
       require(canRead)
-      reads += addr -> UInt()
+      reads += addr -> Wire(UInt())
       reads.last._2 := rf(~addr)
       reads.last._2
     }
@@ -109,7 +109,7 @@ class Datapath extends CoreModule
     }
   }
 
-  val bypass = Vec.fill(NBYP)(Bits())
+  val bypass = Wire(Vec(Bits(), NBYP))
   bypass(BYP_0) := Bits(0)
   bypass(BYP_EX) := mem_reg_wdata
   bypass(BYP_MEM) := wb_reg_wdata
@@ -198,7 +198,7 @@ class Datapath extends CoreModule
   val dmem_resp_valid = io.dmem.resp.valid && io.dmem.resp.bits.has_data
   val dmem_resp_replay = io.dmem.resp.bits.replay && io.dmem.resp.bits.has_data
 
-  val ll_wdata = Bits()
+  val ll_wdata = Wire(Bits())
   div.io.resp.ready := io.ctrl.ll_ready
   ll_wdata := div.io.resp.bits.data
   io.ctrl.ll_waddr := div.io.resp.bits.tag
diff --git a/rocket/src/main/scala/fpu.scala b/rocket/src/main/scala/fpu.scala
index 0194ba4c..9a444fb9 100644
--- a/rocket/src/main/scala/fpu.scala
+++ b/rocket/src/main/scala/fpu.scala
@@ -248,7 +248,7 @@ class IntToFP(val latency: Int) extends Module
 
   val in = Pipe(io.in)
 
-  val mux = new FPResult
+  val mux = Wire(new FPResult)
   mux.exc := Bits(0)
   mux.data := hardfloat.floatNToRecodedFloatN(in.bits.in1, 52, 12)
   when (in.bits.single) {
@@ -299,7 +299,7 @@ class FPToFP(val latency: Int) extends Module
   val isMax = in.bits.rm(0)
   val isLHS = isnan2 || isMax != io.lt && !isnan1
 
-  val mux = new FPResult
+  val mux = Wire(new FPResult)
   mux.exc := minmax_exc
   mux.data := in.bits.in2
 
@@ -347,7 +347,7 @@ class FPUFMAPipe(val latency: Int, sigWidth: Int, expWidth: Int) extends Module
   fma.io.b := in.in2
   fma.io.c := in.in3
 
-  val res = new FPResult
+  val res = Wire(new FPResult)
   res.data := fma.io.out
   res.exc := fma.io.exceptionFlags
   io.out := Pipe(valid, res, latency-1)
@@ -404,7 +404,7 @@ class FPU extends Module
   val ex_rs1::ex_rs2::ex_rs3::Nil = Seq(ex_ra1, ex_ra2, ex_ra3).map(regfile(_))
   val ex_rm = Mux(ex_reg_inst(14,12) === Bits(7), io.dpath.fcsr_rm, ex_reg_inst(14,12))
 
-  val req = new FPInput
+  val req = Wire(new FPInput)
   req := ex_ctrl
   req.rm := ex_rm
   req.in1 := ex_rs1
@@ -441,8 +441,8 @@ class FPU extends Module
   val divSqrt_outValid = divSqrt.io.outValid_div || divSqrt.io.outValid_sqrt
   val divSqrt_wen = Reg(next=Bool(false))
   val divSqrt_waddr = Reg(Bits())
-  val divSqrt_wdata = Bits()
-  val divSqrt_flags = Bits()
+  val divSqrt_wdata = Wire(Bits())
+  val divSqrt_flags = Wire(Bits())
   val divSqrt_in_flight = Reg(init=Bool(false))
 
   // writeback arbitration
diff --git a/rocket/src/main/scala/icache.scala b/rocket/src/main/scala/icache.scala
index 59fc041c..4a4436a6 100644
--- a/rocket/src/main/scala/icache.scala
+++ b/rocket/src/main/scala/icache.scala
@@ -158,11 +158,11 @@ class ICache extends FrontendModule
   val state = Reg(init=s_ready)
   val invalidated = Reg(Bool())
   val stall = !io.resp.ready
-  val rdy = Bool()
+  val rdy = Wire(Bool())
 
   val s2_valid = Reg(init=Bool(false))
   val s2_addr = Reg(UInt(width = paddrBits))
-  val s2_any_tag_hit = Bool()
+  val s2_any_tag_hit = Wire(Bool())
 
   val s1_valid = Reg(init=Bool(false))
   val s1_pgoff = Reg(UInt(width = pgIdxBits))
@@ -212,13 +212,13 @@ class ICache extends FrontendModule
     vb_array := Bits(0)
     invalidated := Bool(true)
   }
-  val s2_disparity = Vec.fill(nWays){Bool()}
+  val s2_disparity = Wire(Vec(Bool(), nWays))
   for (i <- 0 until nWays)
     when (s2_valid && s2_disparity(i)) { vb_array := vb_array.bitSet(Cat(UInt(i), s2_idx), Bool(false)) }
 
-  val s1_tag_match = Vec.fill(nWays){Bool()}
-  val s2_tag_hit = Vec.fill(nWays){Bool()}
-  val s2_dout = Reg(Vec.fill(nWays){Bits()})
+  val s1_tag_match = Wire(Vec(Bool(), nWays))
+  val s2_tag_hit = Wire(Vec(Bool(), nWays))
+  val s2_dout = Reg(Vec(Bits(), nWays))
 
   for (i <- 0 until nWays) {
     val s1_vb = !io.invalidate && vb_array(Cat(UInt(i), s1_pgoff(untagBits-1,blockOffBits))).toBool
diff --git a/rocket/src/main/scala/nbdcache.scala b/rocket/src/main/scala/nbdcache.scala
index 9c822d50..4b191db6 100644
--- a/rocket/src/main/scala/nbdcache.scala
+++ b/rocket/src/main/scala/nbdcache.scala
@@ -108,7 +108,7 @@ class L1MetaWriteReq extends
 
 object L1Metadata {
   def apply(tag: Bits, coh: ClientMetadata) = {
-    val meta = new L1Metadata
+    val meta = Wire(new L1Metadata)
     meta.tag := tag
     meta.coh := coh
     meta
@@ -303,12 +303,12 @@ class MSHRFile extends L1HellaCacheModule {
   val sdq = Mem(io.req.bits.data, sdqDepth)
   when (sdq_enq) { sdq(sdq_alloc_id) := io.req.bits.data }
 
-  val idxMatch = Vec.fill(nMSHRs){Bool()}
-  val tagList = Vec.fill(nMSHRs){Bits()}
+  val idxMatch = Wire(Vec(Bool(), nMSHRs))
+  val tagList = Wire(Vec(Bits(), nMSHRs))
   val tag_match = Mux1H(idxMatch, tagList) === io.req.bits.addr >> untagBits
 
-  val wbTagList = Vec.fill(nMSHRs){Bits()}
-  val refillMux = Vec.fill(nMSHRs){new L1RefillReq}
+  val wbTagList = Wire(Vec(Bits(), nMSHRs))
+  val refillMux = Wire(Vec(new L1RefillReq, nMSHRs))
   val meta_read_arb = Module(new Arbiter(new L1MetaReadReq, nMSHRs))
   val meta_write_arb = Module(new Arbiter(new L1MetaWriteReq, nMSHRs))
   val mem_req_arb = Module(new LockingArbiter(
@@ -548,7 +548,7 @@ class DataArray extends L1HellaCacheModule {
     for (w <- 0 until nWays by rowWords) {
       val wway_en = io.write.bits.way_en(w+rowWords-1,w)
       val rway_en = io.read.bits.way_en(w+rowWords-1,w)
-      val resp = Vec.fill(rowWords){Bits(width = encRowBits)}
+      val resp = Wire(Vec(Bits(width = encRowBits), rowWords))
       val r_raddr = RegEnable(io.read.bits.addr, io.read.valid)
       for (p <- 0 until resp.size) {
         val array = SeqMem(Bits(width=encRowBits), nSets*refillCycles)
@@ -610,8 +610,8 @@ class HellaCache extends L1HellaCacheModule {
   val s2_valid = Reg(next=s1_valid_masked, init=Bool(false))
   val s2_req = Reg(io.cpu.req.bits)
   val s2_replay = Reg(next=s1_replay, init=Bool(false)) && s2_req.cmd != M_NOP
-  val s2_recycle = Bool()
-  val s2_valid_masked = Bool()
+  val s2_recycle = Wire(Bool())
+  val s2_valid_masked = Wire(Bool())
 
   val s3_valid = Reg(init=Bool(false))
   val s3_req = Reg(io.cpu.req.bits)
@@ -747,7 +747,7 @@ class HellaCache extends L1HellaCacheModule {
   }
   when (io.cpu.invalidate_lr) { lrsc_count := 0 }
 
-  val s2_data = Vec.fill(nWays){Bits(width = encRowBits)}
+  val s2_data = Wire(Vec(Bits(width=encRowBits), nWays))
   for (w <- 0 until nWays) {
     val regs = Reg(Vec.fill(rowWords){Bits(width = encDataBits)})
     val en1 = s1_clk_en && s1_tag_eq_way(w)
diff --git a/rocket/src/main/scala/ptw.scala b/rocket/src/main/scala/ptw.scala
index 56cb484c..69fbf57e 100644
--- a/rocket/src/main/scala/ptw.scala
+++ b/rocket/src/main/scala/ptw.scala
@@ -109,8 +109,7 @@ class PTW(n: Int) extends CoreModule
     r_pte := pte
   }
 
-  val pte_wdata = new PTE
-  pte_wdata := new PTE().fromBits(0)
+  val pte_wdata = Wire(init=new PTE().fromBits(0))
   pte_wdata.r := true
   pte_wdata.d := r_req.store