riscv/rocket-chip
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Add Wire() wrap

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This commit is contained in:
Andrew Waterman
2015-07-15 20:24:18 -07:00
parent 5b7f3c3006
commit ac6e73e317
8 changed files with 38 additions and 42 deletions
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4
rocket/src/main/scala/btb.scala
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@ -56,7 +56,7 @@ class BHTResp extends Bundle with BTBParameters {
class BHT(nbht: Int) {
val nbhtbits = log2Up(nbht)
def get(addr: UInt, update: Bool): BHTResp = {
val res = new BHTResp
val res = Wire(new BHTResp)
val index = addr(nbhtbits+1,2) ^ history
res.value := table(index)
res.history := history
@ -178,7 +178,7 @@ class BTB(updates_out_of_order: Boolean = false) extends Module with BTBParamete
val useUpdatePageHit = updatePageHit.orR
val doIdxPageRepl = !useUpdatePageHit
val idxPageRepl = UInt()
val idxPageRepl = Wire(UInt())
val idxPageUpdateOH = Mux(useUpdatePageHit, updatePageHit, idxPageRepl)
val idxPageUpdate = OHToUInt(idxPageUpdateOH)
val idxPageReplEn = Mux(doIdxPageRepl, idxPageRepl, UInt(0))