Async Reg: Doesn't properly reset for Verilator.

vsrc/AsyncResetReg.v

@@ -45,21 +45,28 @@ module AsyncResetReg (
                       input      clk,
                       input      rst);
    
+   initial begin
 `ifdef RANDOMIZE
       integer                       initvar;
       reg [31:0]                    _RAND;
-   initial begin
+      _RAND = {1{$random}};
+`endif
+      if (rst) begin
+`ifdef verilator
+      q = 1'b0;
+`endif
+      end 
+`ifdef RANDOMIZE
  `ifndef verilator
-      #0.002 begin end
  `endif
  `ifdef RANDOMIZE_REG_INIT
-      _RAND = {1{$random}};
+      else begin
-      if (~rst) begin
+         #0.002 begin end
          q = _RAND[0];
       end
  `endif
-   end
 `endif //  `ifdef RANDOMIZE   
+   end
    
    always @(posedge clk or posedge rst) begin