From a97add954a65124fe25e0e3ad45524c6876e62ca Mon Sep 17 00:00:00 2001
From: Megan Wachs <megan@sifive.com>
Date: Fri, 1 Dec 2017 17:43:01 -0800
Subject: [PATCH] Async Reg: Doesn't properly reset for Verilator.

---
 vsrc/AsyncResetReg.v | 31 +++++++++++++++++++------------
 1 file changed, 19 insertions(+), 12 deletions(-)

diff --git a/vsrc/AsyncResetReg.v b/vsrc/AsyncResetReg.v
index aee4b639..f34f4fa9 100644
--- a/vsrc/AsyncResetReg.v
+++ b/vsrc/AsyncResetReg.v
@@ -45,30 +45,37 @@ module AsyncResetReg (
                       input      clk,
                       input      rst);
    
-`ifdef RANDOMIZE
-   integer                       initvar;
-   reg [31:0]                    _RAND;
    initial begin
-`ifndef verilator
-      #0.002 begin end
-`endif
-`ifdef RANDOMIZE_REG_INIT
+`ifdef RANDOMIZE
+      integer                       initvar;
+      reg [31:0]                    _RAND;
       _RAND = {1{$random}};
-      if (~rst) begin
+`endif
+      if (rst) begin
+`ifdef verilator
+      q = 1'b0;
+`endif
+      end 
+`ifdef RANDOMIZE
+ `ifndef verilator
+ `endif
+ `ifdef RANDOMIZE_REG_INIT
+      else begin
+         #0.002 begin end
          q = _RAND[0];
       end
-`endif
+ `endif
+`endif //  `ifdef RANDOMIZE   
    end
-`endif //  `ifdef RANDOMIZE
    
    always @(posedge clk or posedge rst) begin
-      
+
       if (rst) begin
          q <= 1'b0;
       end else if (en) begin
          q <= d;
       end
    end
-   
+
 endmodule // AsyncResetReg