riscv/rocket-chip
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Rename dmem.sret signal to more accurate invalidate_lr

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This commit is contained in:
Christopher Celio
2015-04-11 02:26:33 -07:00
parent 8fc2d38ca9
commit a564f08702
4 changed files with 5 additions and 5 deletions
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2
rocket/src/main/scala/tile.scala
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@ -25,7 +25,7 @@ class RocketTile(resetSignal: Bool = null) extends Tile(resetSignal) {
val ptw = Module(new PTW(params(NPTWPorts)))
val core = Module(new Core, { case CoreName => "Rocket" })
dcache.io.cpu.sret := core.io.dmem.sret // Bypass sret to dcache
dcache.io.cpu.invalidate_lr := core.io.dmem.invalidate_lr // Bypass signal to dcache
val dcArb = Module(new HellaCacheArbiter(params(NDCachePorts)))
dcArb.io.requestor(0) <> ptw.io.mem
dcArb.io.requestor(1) <> core.io.dmem