riscv/rocket-chip
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Rename dmem.sret signal to more accurate invalidate_lr

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This commit is contained in:
Christopher Celio
2015-04-11 02:26:33 -07:00
parent 8fc2d38ca9
commit a564f08702
4 changed files with 5 additions and 5 deletions
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rocket/src/main/scala/ctrl.scala
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@ -674,7 +674,7 @@ class Control extends CoreModule
io.dmem.req.bits.cmd := ex_ctrl.mem_cmd
io.dmem.req.bits.typ := ex_ctrl.mem_type
io.dmem.req.bits.phys := Bool(false)
io.dmem.sret := wb_xcpt // obviously not an sret, but sufficient
io.dmem.invalidate_lr := wb_xcpt
io.rocc.cmd.valid := wb_rocc_val
io.rocc.exception := wb_xcpt && io.dpath.status.xs.orR