From a0378c5d2f37cf43c620717121e77af01513318b Mon Sep 17 00:00:00 2001
From: Andrew Waterman <waterman@eecs.berkeley.edu>
Date: Mon, 16 Apr 2012 22:28:00 -0700
Subject: [PATCH] remove faulting TLB entry after page fault

this vastly reduces the frequency with which the TLB must be flushed
---
 rocket/src/main/scala/dtlb.scala | 1 +
 rocket/src/main/scala/itlb.scala | 7 ++++++-
 2 files changed, 7 insertions(+), 1 deletion(-)

diff --git a/rocket/src/main/scala/dtlb.scala b/rocket/src/main/scala/dtlb.scala
index 99f7f385..c7b92662 100644
--- a/rocket/src/main/scala/dtlb.scala
+++ b/rocket/src/main/scala/dtlb.scala
@@ -79,6 +79,7 @@ class rocketDTLB(entries: Int) extends Component
   
   val lookup_tag = Cat(r_cpu_req_asid, r_cpu_req_vpn);
   tag_cam.io.clear      := io.invalidate;
+  tag_cam.io.clear_hit  := io.cpu_resp.xcpt_ld || io.cpu_resp.xcpt_st || io.cpu_resp.xcpt_pf
   tag_cam.io.tag        := lookup_tag;
   tag_cam.io.write      := io.ptw.resp_val || io.ptw.resp_err;
   tag_cam.io.write_tag  := r_refill_tag;
diff --git a/rocket/src/main/scala/itlb.scala b/rocket/src/main/scala/itlb.scala
index 2178aa00..016a2efb 100644
--- a/rocket/src/main/scala/itlb.scala
+++ b/rocket/src/main/scala/itlb.scala
@@ -7,6 +7,7 @@ import scala.math._;
 
 class ioCAM(entries: Int, addr_bits: Int, tag_bits: Int) extends Bundle {
     val clear        = Bool(INPUT);
+    val clear_hit    = Bool(INPUT)
     val tag          = Bits(tag_bits, INPUT);
     val hit          = Bool(OUTPUT);
     val hit_addr     = UFix(addr_bits, OUTPUT);
@@ -21,17 +22,20 @@ class rocketCAM(entries: Int, tag_bits: Int) extends Component {
   val addr_bits = ceil(log(entries)/log(2)).toInt;
   val io = new ioCAM(entries, addr_bits, tag_bits);
   val cam_tags = Mem(entries, io.write, io.write_addr, io.write_tag);
+  val mux = (new Mux1H(entries)) { Bits(width = addr_bits) }
 
   val vb_array = Reg(resetVal = Bits(0, entries));
   when (io.clear) {
     vb_array := Bits(0, entries);
   }
+  .elsewhen (io.clear_hit) {
+    vb_array := vb_array & ~mux.io.sel.toBits
+  }
   .elsewhen (io.write) {
     vb_array := vb_array.bitSet(io.write_addr, Bool(true));
   }
   
   var l_hit = Bool(false)
-  val mux = (new Mux1H(entries)) { Bits(width = addr_bits) }
   for (i <- 0 to entries-1) {
     val my_hit = vb_array(UFix(i)).toBool && (cam_tags(UFix(i)) === io.tag)
     l_hit = l_hit || my_hit
@@ -114,6 +118,7 @@ class rocketITLB(entries: Int) extends Component
   
   val lookup_tag = Cat(r_cpu_req_asid, r_cpu_req_vpn);
   tag_cam.io.clear      := io.cpu.invalidate;
+  tag_cam.io.clear_hit  := io.cpu.exception
   tag_cam.io.tag        := lookup_tag;
   tag_cam.io.write      := io.ptw.resp_val || io.ptw.resp_err;
   tag_cam.io.write_tag  := r_refill_tag;