riscv/rocket-chip
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more itlb integration & cleanup

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This commit is contained in:
Rimas Avizienis 2011-11-09 23:18:14 -08:00
parent c29d2821b4
commit 9aca403aa8
6 changed files with 13 additions and 11 deletions
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4
rocket/src/main/scala/arbiter.scala
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@ -9,7 +9,7 @@ class ioMem() extends Bundle
val req_val = Bool('output); val req_val = Bool('output);
val req_rdy = Bool('input); val req_rdy = Bool('input);
val req_rw = Bool('output); val req_rw = Bool('output);
val req_addr = UFix(32, 'output); val req_addr = UFix(PADDR_BITS, 'output);
val req_wdata = Bits(128, 'output); val req_wdata = Bits(128, 'output);
val req_tag = Bits(4, 'output); val req_tag = Bits(4, 'output);
@ -67,7 +67,7 @@ class rocketMemArbiter extends Component {
io.dcache.resp_data := io.mem.resp_data; io.dcache.resp_data := io.mem.resp_data;
io.icache.resp_tag := io.mem.resp_tag(2,0); io.icache.resp_tag := io.mem.resp_tag(2,0);
io.dcache.resp_tag := io.mem.resp_tag(2,0); // io.dcache.resp_tag := io.mem.resp_tag(2,0);
} }

2
rocket/src/main/scala/dcache.scala
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@ -29,7 +29,7 @@ class ioDcache(view: List[String] = null) extends Bundle(view) {
val req_wdata = Bits(128, 'input); val req_wdata = Bits(128, 'input);
val req_rw = Bool('input); val req_rw = Bool('input);
val resp_data = Bits(128, 'output); val resp_data = Bits(128, 'output);
val resp_tag = Bits(3, 'output); // val resp_tag = Bits(3, 'output);
val resp_val = Bool('output); val resp_val = Bool('output);
} }

6
rocket/src/main/scala/dpath.scala
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@ -49,7 +49,7 @@ class rocketDpath extends Component
val rfile = new rocketDpathRegfile(); val rfile = new rocketDpathRegfile();
// instruction fetch definitions // instruction fetch definitions
val if_reg_pc = Reg(width = 32, resetVal = UFix(0, 32)); val if_reg_pc = Reg(resetVal = UFix(0,VADDR_BITS));
// instruction decode definitions // instruction decode definitions
val id_reg_valid = Reg(resetVal = Bool(false)); val id_reg_valid = Reg(resetVal = Bool(false));
@ -128,8 +128,8 @@ class rocketDpath extends Component
Cat(Fill(52, ex_reg_inst(31)), ex_reg_inst(31,27), ex_reg_inst(16,10)); Cat(Fill(52, ex_reg_inst(31)), ex_reg_inst(31,27), ex_reg_inst(16,10));
val branch_adder_rhs = val branch_adder_rhs =
Mux(io.ctrl.sel_pc === PC_BR, Cat(ex_sign_extend_split(30,0), UFix(0, 1)), Mux(io.ctrl.sel_pc === PC_BR, Cat(ex_sign_extend_split(41,0), UFix(0, 1)),
Cat(Fill(6, ex_reg_inst(31)), ex_reg_inst(31,7), UFix(0, 1))); Cat(Fill(17, ex_reg_inst(31)), ex_reg_inst(31,7), UFix(0, 1)));
val ex_branch_target = ex_reg_pc + branch_adder_rhs.toUFix; val ex_branch_target = ex_reg_pc + branch_adder_rhs.toUFix;

5
rocket/src/main/scala/dpath_alu.scala
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@ -18,7 +18,8 @@ class ioALU extends Bundle(){
class rocketDpathALU extends Component class rocketDpathALU extends Component
{ {
override val io = new ioALU(); val io = new ioALU();
val out64 = val out64 =
MuxCase(Fix(0, 64), Array( MuxCase(Fix(0, 64), Array(
(io.fn === FN_ADD) -> (io.in1 + io.in2).toFix, (io.fn === FN_ADD) -> (io.in1 + io.in2).toFix,
@ -34,7 +35,7 @@ class rocketDpathALU extends Component
(io.fn === FN_SRA) -> (io.in1.toFix >>> io.shamt))); (io.fn === FN_SRA) -> (io.in1.toFix >>> io.shamt)));
io.out := MuxLookup(io.dw, Fix(0, 64), Array( io.out := MuxLookup(io.dw, Fix(0, 64), Array(
DW_64 -> out64, DW_64 -> out64(63,0),
DW_32 -> Cat(Fill(32, out64(31)), out64(31,0)).toFix)).toUFix; DW_32 -> Cat(Fill(32, out64(31)), out64(31,0)).toFix)).toUFix;
} }

3
rocket/src/main/scala/icache_prefetch.scala
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@ -2,11 +2,12 @@ package Top {
import Chisel._; import Chisel._;
import Node._; import Node._;
import Constants._;
import queues._; import queues._;
class ioIPrefetcherMem(view: List[String] = null) extends Bundle (view) class ioIPrefetcherMem(view: List[String] = null) extends Bundle (view)
{ {
val req_addr = UFix(32, 'output); val req_addr = UFix(PADDR_BITS, 'output);
val req_val = Bool('output); val req_val = Bool('output);
val req_rdy = Bool('input); val req_rdy = Bool('input);
val req_tag = Bits(3, 'output); val req_tag = Bits(3, 'output);

4
rocket/src/main/scala/ptw.scala
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@ -83,8 +83,8 @@ class rocketPTW extends Component
io.itlb.resp_err := (state === s_error); io.itlb.resp_err := (state === s_error);
io.itlb.resp_perm := r_resp_perm; io.itlb.resp_perm := r_resp_perm;
io.itlb.resp_ppn := io.itlb.resp_ppn :=
Mux(state === s_l1_fake, Cat(r_resp_ppn(PPN_BITS-1, PPN_BITS-7), r_req_vpn(VPN_BITS-8, 0)), Mux(state === s_l1_fake, Cat(r_resp_ppn(PPN_BITS-1, PPN_BITS-7), r_req_vpn(VPN_BITS-11, 0)),
Mux(state === s_l2_fake, Cat(r_resp_ppn(PPN_BITS-1, PPN_BITS-17), r_req_vpn(VPN_BITS-18, 0)), Mux(state === s_l2_fake, Cat(r_resp_ppn(PPN_BITS-1, PPN_BITS-17), r_req_vpn(VPN_BITS-21, 0)),
r_resp_ppn)); r_resp_ppn));
val resp_ptd = (io.dmem.resp_data(1,0) === Bits(1,2)); val resp_ptd = (io.dmem.resp_data(1,0) === Bits(1,2));