diff --git a/rocket/src/main/scala/arbiter.scala b/rocket/src/main/scala/arbiter.scala
index eaf0241d..7e2ca8b4 100644
--- a/rocket/src/main/scala/arbiter.scala
+++ b/rocket/src/main/scala/arbiter.scala
@@ -9,7 +9,7 @@ class ioMem() extends Bundle
   val req_val = Bool('output);
   val req_rdy = Bool('input);
   val req_rw  = Bool('output);
-  val req_addr = UFix(32, 'output);
+  val req_addr = UFix(PADDR_BITS, 'output);
   val req_wdata = Bits(128, 'output);
   val req_tag = Bits(4, 'output);
   
@@ -67,7 +67,7 @@ class rocketMemArbiter extends Component {
   io.dcache.resp_data := io.mem.resp_data;
   
   io.icache.resp_tag := io.mem.resp_tag(2,0);
-  io.dcache.resp_tag := io.mem.resp_tag(2,0);
+//   io.dcache.resp_tag := io.mem.resp_tag(2,0);
 
 }
 
diff --git a/rocket/src/main/scala/dcache.scala b/rocket/src/main/scala/dcache.scala
index fcd10394..644a73b3 100644
--- a/rocket/src/main/scala/dcache.scala
+++ b/rocket/src/main/scala/dcache.scala
@@ -29,7 +29,7 @@ class ioDcache(view: List[String] = null) extends Bundle(view) {
   val req_wdata = Bits(128, 'input);
   val req_rw    = Bool('input);
   val resp_data = Bits(128, 'output);
-  val resp_tag  = Bits(3, 'output);
+//   val resp_tag  = Bits(3, 'output);
   val resp_val  = Bool('output);
 }
 
diff --git a/rocket/src/main/scala/dpath.scala b/rocket/src/main/scala/dpath.scala
index d687bb8d..a759b8ea 100644
--- a/rocket/src/main/scala/dpath.scala
+++ b/rocket/src/main/scala/dpath.scala
@@ -49,7 +49,7 @@ class rocketDpath extends Component
 	val rfile = new rocketDpathRegfile();
 
   // instruction fetch definitions
-  val if_reg_pc     = Reg(width = 32, resetVal = UFix(0, 32));
+  val if_reg_pc     = Reg(resetVal = UFix(0,VADDR_BITS));
 
   // instruction decode definitions
   val id_reg_valid     = Reg(resetVal = Bool(false));
@@ -128,8 +128,8 @@ class rocketDpath extends Component
     Cat(Fill(52, ex_reg_inst(31)), ex_reg_inst(31,27), ex_reg_inst(16,10));
 
   val branch_adder_rhs =
-    Mux(io.ctrl.sel_pc === PC_BR, Cat(ex_sign_extend_split(30,0), UFix(0, 1)),
-        Cat(Fill(6, ex_reg_inst(31)), ex_reg_inst(31,7),          UFix(0, 1)));
+    Mux(io.ctrl.sel_pc === PC_BR, Cat(ex_sign_extend_split(41,0), UFix(0, 1)),
+        Cat(Fill(17, ex_reg_inst(31)), ex_reg_inst(31,7),          UFix(0, 1)));
 
   val ex_branch_target = ex_reg_pc + branch_adder_rhs.toUFix;
 
diff --git a/rocket/src/main/scala/dpath_alu.scala b/rocket/src/main/scala/dpath_alu.scala
index d7ae1e90..6c4eadfd 100644
--- a/rocket/src/main/scala/dpath_alu.scala
+++ b/rocket/src/main/scala/dpath_alu.scala
@@ -18,7 +18,8 @@ class ioALU extends Bundle(){
 
 class rocketDpathALU extends Component
 {
-  override val io = new ioALU();
+  val io = new ioALU();
+  
   val out64 =
     MuxCase(Fix(0, 64), Array(
       (io.fn === FN_ADD) ->                   (io.in1 + io.in2).toFix,
@@ -34,7 +35,7 @@ class rocketDpathALU extends Component
       (io.fn === FN_SRA) ->                   (io.in1.toFix >>> io.shamt)));
       
   io.out := MuxLookup(io.dw, Fix(0, 64), Array(
-              DW_64 -> out64,
+              DW_64 -> out64(63,0),
               DW_32 -> Cat(Fill(32, out64(31)), out64(31,0)).toFix)).toUFix;
 
 }
diff --git a/rocket/src/main/scala/icache_prefetch.scala b/rocket/src/main/scala/icache_prefetch.scala
index 1c1219e3..fe7b761c 100644
--- a/rocket/src/main/scala/icache_prefetch.scala
+++ b/rocket/src/main/scala/icache_prefetch.scala
@@ -2,11 +2,12 @@ package Top {
 
 import Chisel._;
 import Node._;
+import Constants._;
 import queues._;
 
 class ioIPrefetcherMem(view: List[String] = null) extends Bundle (view)
 {
-  val req_addr  = UFix(32, 'output);
+  val req_addr  = UFix(PADDR_BITS, 'output);
   val req_val   = Bool('output);
   val req_rdy   = Bool('input);
   val req_tag   = Bits(3, 'output);
diff --git a/rocket/src/main/scala/ptw.scala b/rocket/src/main/scala/ptw.scala
index 18fc8912..89170884 100644
--- a/rocket/src/main/scala/ptw.scala
+++ b/rocket/src/main/scala/ptw.scala
@@ -83,8 +83,8 @@ class rocketPTW extends Component
   io.itlb.resp_err  := (state === s_error);
   io.itlb.resp_perm := r_resp_perm;
   io.itlb.resp_ppn  :=
-    Mux(state === s_l1_fake, Cat(r_resp_ppn(PPN_BITS-1, PPN_BITS-7),  r_req_vpn(VPN_BITS-8, 0)),
-    Mux(state === s_l2_fake, Cat(r_resp_ppn(PPN_BITS-1, PPN_BITS-17), r_req_vpn(VPN_BITS-18, 0)),
+    Mux(state === s_l1_fake, Cat(r_resp_ppn(PPN_BITS-1, PPN_BITS-7),  r_req_vpn(VPN_BITS-11, 0)),
+    Mux(state === s_l2_fake, Cat(r_resp_ppn(PPN_BITS-1, PPN_BITS-17), r_req_vpn(VPN_BITS-21, 0)),
       r_resp_ppn));
 
   val resp_ptd = (io.dmem.resp_data(1,0) === Bits(1,2));