riscv/rocket-chip
1
0
Fork 0
Code Releases Activity

move ReorderQueue to utils.scala

Browse Source
This commit is contained in:
Howard Mao 2015-10-13 09:49:22 -07:00
parent 0fe16ac1c0
commit 993ed86198
2 changed files with 41 additions and 41 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

41
uncore/src/main/scala/tilelink.scala
View File

@ -1241,47 +1241,6 @@ trait HasDataBeatCounters {
}
}
class ReorderQueueWrite[T <: Data](dType: T, tagWidth: Int) extends Bundle {
val data = dType.cloneType
val tag = UInt(width = tagWidth)
override def cloneType =
new ReorderQueueWrite(dType, tagWidth).asInstanceOf[this.type]
}
class ReorderQueue[T <: Data](dType: T, tagWidth: Int, size: Int)
extends Module {
val io = new Bundle {
val enq = Decoupled(new ReorderQueueWrite(dType, tagWidth)).flip
val deq = new Bundle {
val valid = Bool(INPUT)
val tag = UInt(INPUT, tagWidth)
val data = dType.cloneType.asOutput
}
val full = Bool(OUTPUT)
}
val roq_data = Reg(Vec(dType.cloneType, size))
val roq_tags = Reg(Vec(UInt(width = tagWidth), size))
val roq_free = Reg(init = Vec.fill(size)(Bool(true)))
val roq_enq_addr = PriorityEncoder(roq_free)
val roq_deq_addr = PriorityEncoder(roq_tags.map(_ === io.deq.tag))
io.enq.ready := roq_free.reduce(_ || _)
io.deq.data := roq_data(roq_deq_addr)
when (io.enq.valid && io.enq.ready) {
roq_data(roq_enq_addr) := io.enq.bits.data
roq_tags(roq_enq_addr) := io.enq.bits.tag
roq_free(roq_enq_addr) := Bool(false)
}
when (io.deq.valid) {
roq_free(roq_deq_addr) := Bool(true)
}
}
class ClientTileLinkIOUnwrapperInfo extends Bundle {
val voluntary = Bool()
val builtin = Bool()

41
uncore/src/main/scala/util.scala
View File

@ -104,3 +104,44 @@ object FlowThroughSerializer {
fs.io.out
}
}
class ReorderQueueWrite[T <: Data](dType: T, tagWidth: Int) extends Bundle {
val data = dType.cloneType
val tag = UInt(width = tagWidth)
override def cloneType =
new ReorderQueueWrite(dType, tagWidth).asInstanceOf[this.type]
}
class ReorderQueue[T <: Data](dType: T, tagWidth: Int, size: Int)
extends Module {
val io = new Bundle {
val enq = Decoupled(new ReorderQueueWrite(dType, tagWidth)).flip
val deq = new Bundle {
val valid = Bool(INPUT)
val tag = UInt(INPUT, tagWidth)
val data = dType.cloneType.asOutput
}
val full = Bool(OUTPUT)
}
val roq_data = Reg(Vec(dType.cloneType, size))
val roq_tags = Reg(Vec(UInt(width = tagWidth), size))
val roq_free = Reg(init = Vec.fill(size)(Bool(true)))
val roq_enq_addr = PriorityEncoder(roq_free)
val roq_deq_addr = PriorityEncoder(roq_tags.map(_ === io.deq.tag))
io.enq.ready := roq_free.reduce(_ || _)
io.deq.data := roq_data(roq_deq_addr)
when (io.enq.valid && io.enq.ready) {
roq_data(roq_enq_addr) := io.enq.bits.data
roq_tags(roq_enq_addr) := io.enq.bits.tag
roq_free(roq_enq_addr) := Bool(false)
}
when (io.deq.valid) {
roq_free(roq_deq_addr) := Bool(true)
}
}