From 993ed86198391efec3393a35e7756c673e4999be Mon Sep 17 00:00:00 2001
From: Howard Mao <zhehao.mao@gmail.com>
Date: Tue, 13 Oct 2015 09:49:22 -0700
Subject: [PATCH] move ReorderQueue to utils.scala

---
 uncore/src/main/scala/tilelink.scala | 41 ----------------------------
 uncore/src/main/scala/util.scala     | 41 ++++++++++++++++++++++++++++
 2 files changed, 41 insertions(+), 41 deletions(-)

diff --git a/uncore/src/main/scala/tilelink.scala b/uncore/src/main/scala/tilelink.scala
index f6dbc54d..36520946 100644
--- a/uncore/src/main/scala/tilelink.scala
+++ b/uncore/src/main/scala/tilelink.scala
@@ -1241,47 +1241,6 @@ trait HasDataBeatCounters {
   }
 }
 
-class ReorderQueueWrite[T <: Data](dType: T, tagWidth: Int) extends Bundle {
-  val data = dType.cloneType
-  val tag = UInt(width = tagWidth)
-
-  override def cloneType =
-    new ReorderQueueWrite(dType, tagWidth).asInstanceOf[this.type]
-}
-
-class ReorderQueue[T <: Data](dType: T, tagWidth: Int, size: Int)
-    extends Module {
-  val io = new Bundle {
-    val enq = Decoupled(new ReorderQueueWrite(dType, tagWidth)).flip
-    val deq = new Bundle {
-      val valid = Bool(INPUT)
-      val tag = UInt(INPUT, tagWidth)
-      val data = dType.cloneType.asOutput
-    }
-    val full = Bool(OUTPUT)
-  }
-
-  val roq_data = Reg(Vec(dType.cloneType, size))
-  val roq_tags = Reg(Vec(UInt(width = tagWidth), size))
-  val roq_free = Reg(init = Vec.fill(size)(Bool(true)))
-
-  val roq_enq_addr = PriorityEncoder(roq_free)
-  val roq_deq_addr = PriorityEncoder(roq_tags.map(_ === io.deq.tag))
-
-  io.enq.ready := roq_free.reduce(_ || _)
-  io.deq.data := roq_data(roq_deq_addr)
-
-  when (io.enq.valid && io.enq.ready) {
-    roq_data(roq_enq_addr) := io.enq.bits.data
-    roq_tags(roq_enq_addr) := io.enq.bits.tag
-    roq_free(roq_enq_addr) := Bool(false)
-  }
-
-  when (io.deq.valid) {
-    roq_free(roq_deq_addr) := Bool(true)
-  }
-}
-
 class ClientTileLinkIOUnwrapperInfo extends Bundle {
   val voluntary = Bool()
   val builtin = Bool()
diff --git a/uncore/src/main/scala/util.scala b/uncore/src/main/scala/util.scala
index 8fb21f2e..ab4f9947 100644
--- a/uncore/src/main/scala/util.scala
+++ b/uncore/src/main/scala/util.scala
@@ -104,3 +104,44 @@ object FlowThroughSerializer {
     fs.io.out
   }
 } 
+
+class ReorderQueueWrite[T <: Data](dType: T, tagWidth: Int) extends Bundle {
+  val data = dType.cloneType
+  val tag = UInt(width = tagWidth)
+
+  override def cloneType =
+    new ReorderQueueWrite(dType, tagWidth).asInstanceOf[this.type]
+}
+
+class ReorderQueue[T <: Data](dType: T, tagWidth: Int, size: Int)
+    extends Module {
+  val io = new Bundle {
+    val enq = Decoupled(new ReorderQueueWrite(dType, tagWidth)).flip
+    val deq = new Bundle {
+      val valid = Bool(INPUT)
+      val tag = UInt(INPUT, tagWidth)
+      val data = dType.cloneType.asOutput
+    }
+    val full = Bool(OUTPUT)
+  }
+
+  val roq_data = Reg(Vec(dType.cloneType, size))
+  val roq_tags = Reg(Vec(UInt(width = tagWidth), size))
+  val roq_free = Reg(init = Vec.fill(size)(Bool(true)))
+
+  val roq_enq_addr = PriorityEncoder(roq_free)
+  val roq_deq_addr = PriorityEncoder(roq_tags.map(_ === io.deq.tag))
+
+  io.enq.ready := roq_free.reduce(_ || _)
+  io.deq.data := roq_data(roq_deq_addr)
+
+  when (io.enq.valid && io.enq.ready) {
+    roq_data(roq_enq_addr) := io.enq.bits.data
+    roq_tags(roq_enq_addr) := io.enq.bits.tag
+    roq_free(roq_enq_addr) := Bool(false)
+  }
+
+  when (io.deq.valid) {
+    roq_free(roq_deq_addr) := Bool(true)
+  }
+}