riscv/rocket-chip
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change dcache tag bits to 7

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This commit is contained in:
Yunsup Lee
2014-02-22 22:53:04 -08:00
parent 8e3ca609f7
commit 97b1841fcf
2 changed files with 2 additions and 1 deletions
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1
rocket/src/main/scala/dpath.scala
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@@ -180,6 +180,7 @@ class Datapath(implicit conf: RocketConfiguration) extends Module
io.dmem.req.bits.addr := Cat(vaSign(ex_rs(0), alu.io.adder_out), alu.io.adder_out(VADDR_BITS-1,0)).toUInt io.dmem.req.bits.addr := Cat(vaSign(ex_rs(0), alu.io.adder_out), alu.io.adder_out(VADDR_BITS-1,0)).toUInt
io.dmem.req.bits.tag := Cat(io.ctrl.ex_waddr, io.ctrl.ex_fp_val) io.dmem.req.bits.tag := Cat(io.ctrl.ex_waddr, io.ctrl.ex_fp_val)
require(io.dmem.req.bits.tag.getWidth >= 6) require(io.dmem.req.bits.tag.getWidth >= 6)
require(conf.dcacheReqTagBits >= 6)
// processor control regfile read // processor control regfile read
val pcr = Module(new CSRFile) val pcr = Module(new CSRFile)

2
rocket/src/main/scala/tile.scala
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@@ -13,7 +13,7 @@ case class RocketConfiguration(tl: TileLinkConfiguration,
fastLoadByte: Boolean = false, fastLoadByte: Boolean = false,
fastMulDiv: Boolean = true) fastMulDiv: Boolean = true)
{ {
val dcacheReqTagBits = 10 // enforce compliance with require() // hue hue hue val dcacheReqTagBits = 7 // enforce compliance with require()
val xprlen = 64 val xprlen = 64
val nxpr = 32 val nxpr = 32
val nxprbits = log2Up(nxpr) val nxprbits = log2Up(nxpr)