diff --git a/rocket/src/main/scala/dpath.scala b/rocket/src/main/scala/dpath.scala
index 381dd1da..f325a0f0 100644
--- a/rocket/src/main/scala/dpath.scala
+++ b/rocket/src/main/scala/dpath.scala
@@ -180,6 +180,7 @@ class Datapath(implicit conf: RocketConfiguration) extends Module
   io.dmem.req.bits.addr := Cat(vaSign(ex_rs(0), alu.io.adder_out), alu.io.adder_out(VADDR_BITS-1,0)).toUInt
   io.dmem.req.bits.tag := Cat(io.ctrl.ex_waddr, io.ctrl.ex_fp_val)
   require(io.dmem.req.bits.tag.getWidth >= 6)
+  require(conf.dcacheReqTagBits >= 6)
 
   // processor control regfile read
   val pcr = Module(new CSRFile)
diff --git a/rocket/src/main/scala/tile.scala b/rocket/src/main/scala/tile.scala
index 1791e6f8..99173748 100644
--- a/rocket/src/main/scala/tile.scala
+++ b/rocket/src/main/scala/tile.scala
@@ -13,7 +13,7 @@ case class RocketConfiguration(tl: TileLinkConfiguration,
                                fastLoadByte: Boolean = false,
                                fastMulDiv: Boolean = true)
 {
-  val dcacheReqTagBits = 10 // enforce compliance with require() // hue hue hue
+  val dcacheReqTagBits = 7 // enforce compliance with require()
   val xprlen = 64
   val nxpr = 32
   val nxprbits = log2Up(nxpr)