change dcache tag bits to 7

rocket/src/main/scala/tile.scala

@@ -13,7 +13,7 @@ case class RocketConfiguration(tl: TileLinkConfiguration,
                                fastLoadByte: Boolean = false,
                                fastMulDiv: Boolean = true)
 {
-  val dcacheReqTagBits = 10 // enforce compliance with require() // hue hue hue
+  val dcacheReqTagBits = 7 // enforce compliance with require()
   val xprlen = 64
   val nxpr = 32
   val nxprbits = log2Up(nxpr)