diff --git a/rocket/src/main/scala/arbiter.scala b/rocket/src/main/scala/arbiter.scala
index b2a8482f..a097b8b1 100644
--- a/rocket/src/main/scala/arbiter.scala
+++ b/rocket/src/main/scala/arbiter.scala
@@ -52,3 +52,16 @@ class HellaCacheArbiter(n: Int) extends Module
     io.requestor(i).replay_next.bits := io.mem.replay_next.bits >> UInt(log2Up(n))
   }
 }
+
+class RocketTileLinkIOArbiter(n: Int) extends TileLinkArbiterLike(n) 
+    with AppendsArbiterId {
+  val io = new Bundle {
+    val in = Vec.fill(n){new HeaderlessTileLinkIO}.flip
+    val out = new HeaderlessTileLinkIO
+  }
+  hookupClientSourceHeaderless(io.in.map(_.acquire), io.out.acquire)
+  hookupClientSourceHeaderless(io.in.map(_.release), io.out.release)
+  hookupFinish(io.in.map(_.finish), io.out.finish)
+  hookupManagerSourceBroadcast(io.in.map(_.probe), io.out.probe)
+  hookupManagerSourceWithId(io.in.map(_.grant), io.out.grant)
+}
diff --git a/rocket/src/main/scala/icache.scala b/rocket/src/main/scala/icache.scala
index ffdcd9ee..b3d40b09 100644
--- a/rocket/src/main/scala/icache.scala
+++ b/rocket/src/main/scala/icache.scala
@@ -45,7 +45,7 @@ class Frontend(btb_updates_out_of_order: Boolean = false) extends FrontendModule
   val io = new Bundle {
     val cpu = new CPUFrontendIO().flip
     val ptw = new TLBPTWIO()
-    val mem = new UncachedTileLinkIO
+    val mem = new HeaderlessUncachedTileLinkIO
   }
 
   val btb = Module(new BTB(btb_updates_out_of_order))
@@ -148,7 +148,7 @@ class ICache extends FrontendModule
     val req = Valid(new ICacheReq).flip
     val resp = Decoupled(new ICacheResp)
     val invalidate = Bool(INPUT)
-    val mem = new UncachedTileLinkIO
+    val mem = new HeaderlessUncachedTileLinkIO
   }
   require(isPow2(nSets) && isPow2(nWays))
   require(isPow2(coreInstBytes))
@@ -273,7 +273,7 @@ class ICache extends FrontendModule
   // output signals
   io.resp.valid := s2_hit
   io.mem.acquire.valid := (state === s_request) && ack_q.io.enq.ready
-  io.mem.acquire.bits.payload := GetBlock(addr_block = s2_addr >> UInt(blockOffBits))
+  io.mem.acquire.bits := GetBlock(addr_block = s2_addr >> UInt(blockOffBits))
   io.mem.finish <> ack_q.io.deq
 
   // control state machine
diff --git a/rocket/src/main/scala/nbdcache.scala b/rocket/src/main/scala/nbdcache.scala
index 9d3ca5b8..7ea62577 100644
--- a/rocket/src/main/scala/nbdcache.scala
+++ b/rocket/src/main/scala/nbdcache.scala
@@ -597,7 +597,7 @@ class HellaCache extends L1HellaCacheModule {
   val io = new Bundle {
     val cpu = (new HellaCacheIO).flip
     val ptw = new TLBPTWIO()
-    val mem = new TileLinkIO
+    val mem = new HeaderlessTileLinkIO
   }
  
   require(params(LRSCCycles) >= 32) // ISA requires 16-insn LRSC sequences to succeed
@@ -802,7 +802,7 @@ class HellaCache extends L1HellaCacheModule {
   mshrs.io.req.bits.data := s2_req.data
   when (mshrs.io.req.fire()) { replacer.miss }
 
-  io.mem.acquire <> DecoupledLogicalNetworkIOWrapper(mshrs.io.mem_req)
+  io.mem.acquire <> mshrs.io.mem_req
 
   // replays
   readArb.io.in(1).valid := mshrs.io.replay.valid
@@ -815,7 +815,7 @@ class HellaCache extends L1HellaCacheModule {
 
   // probes and releases
   val releaseArb = Module(new LockingArbiter(new Release, 2, outerDataBeats, (r: Release) => r.hasMultibeatData()))
-  DecoupledLogicalNetworkIOWrapper(releaseArb.io.out) <> io.mem.release
+  releaseArb.io.out <> io.mem.release
 
   val probe = DecoupledLogicalNetworkIOUnwrapper(io.mem.probe)
   prober.io.req.valid := probe.valid && !lrsc_valid
diff --git a/rocket/src/main/scala/rocc.scala b/rocket/src/main/scala/rocc.scala
index 425c96b5..f1132383 100644
--- a/rocket/src/main/scala/rocc.scala
+++ b/rocket/src/main/scala/rocc.scala
@@ -42,8 +42,8 @@ class RoCCInterface extends Bundle
   val interrupt = Bool(OUTPUT)
   
   // These should be handled differently, eventually
-  val imem = new UncachedTileLinkIO
-  val dmem = new TileLinkIO
+  val imem = new HeaderlessUncachedTileLinkIO
+  val dmem = new HeaderlessTileLinkIO
   val iptw = new TLBPTWIO
   val dptw = new TLBPTWIO
   val pptw = new TLBPTWIO
diff --git a/rocket/src/main/scala/tile.scala b/rocket/src/main/scala/tile.scala
index bb5356ee..cac5e2e4 100644
--- a/rocket/src/main/scala/tile.scala
+++ b/rocket/src/main/scala/tile.scala
@@ -14,7 +14,7 @@ case object BuildRoCC extends Field[Option[() => RoCC]]
 
 abstract class Tile(resetSignal: Bool = null) extends Module(_reset = resetSignal) {
   val io = new Bundle {
-    val tilelink = new TileLinkIO
+    val tilelink = new HeaderlessTileLinkIO
     val host = new HTIFIO
   }
 }
@@ -39,10 +39,10 @@ class RocketTile(resetSignal: Bool = null) extends Tile(resetSignal) {
   core.io.imem <> icache.io.cpu
   core.io.ptw <> ptw.io.dpath
 
-  val memArb = Module(new TileLinkIOArbiterThatAppendsArbiterId(params(NTilePorts)))
+  val memArb = Module(new RocketTileLinkIOArbiter(params(NTilePorts)))
   io.tilelink <> memArb.io.out
   memArb.io.in(0) <> dcache.io.mem
-  memArb.io.in(1) <> TileLinkIOWrapper(icache.io.mem)
+  memArb.io.in(1) <> HeaderlessTileLinkIOWrapper(icache.io.mem)
 
   //If so specified, build an RoCC module and wire it in
   params(BuildRoCC)
@@ -52,7 +52,7 @@ class RocketTile(resetSignal: Bool = null) extends Tile(resetSignal) {
       core.io.rocc <> rocc.io
       dcIF.io.requestor <> rocc.io.mem
       dcArb.io.requestor(2) <> dcIF.io.cache
-      memArb.io.in(2) <> TileLinkIOWrapper(rocc.io.imem)
+      memArb.io.in(2) <> HeaderlessTileLinkIOWrapper(rocc.io.imem)
       memArb.io.in(3) <> rocc.io.dmem
       ptw.io.requestor(2) <> rocc.io.iptw
       ptw.io.requestor(3) <> rocc.io.dptw