diff --git a/uncore/src/main/scala/debug.scala b/uncore/src/main/scala/debug.scala
index df382a59..eb22d2b7 100644
--- a/uncore/src/main/scala/debug.scala
+++ b/uncore/src/main/scala/debug.scala
@@ -802,7 +802,7 @@ class DebugModule ()(implicit val p:cde.Parameters)
     // Inspired by ROMSlave
     val romContents = cfg.debugRomContents.get
     val romByteWidth = tlDataBits / 8
-    val romRows =  Math.ceil((romContents.size + romByteWidth)/romByteWidth).toInt
+    val romRows = (romContents.size + romByteWidth - 1)/romByteWidth
     val romMem = Vec.tabulate(romRows) { ii =>
       val slice = romContents.slice(ii*romByteWidth, (ii+1)*romByteWidth)
       UInt(slice.foldRight(BigInt(0)) { case (x,y) => ((y << 8) + (x.toInt & 0xFF))}, width = romByteWidth*8)
diff --git a/uncore/src/main/scala/rom.scala b/uncore/src/main/scala/rom.scala
index b635e127..1ac56e1d 100644
--- a/uncore/src/main/scala/rom.scala
+++ b/uncore/src/main/scala/rom.scala
@@ -19,7 +19,7 @@ class ROMSlave(contents: Seq[Byte])(implicit val p: Parameters) extends Module
   when (io.acquire.fire()) { addr_beat := io.acquire.bits.addr_beat }
 
   val byteWidth = tlDataBits / 8
-  val rows = (contents.size + byteWidth - 1)/byteWidth + 1
+  val rows = (contents.size + byteWidth - 1)/byteWidth
   val rom = Vec.tabulate(rows) { i =>
     val slice = contents.slice(i*byteWidth, (i+1)*byteWidth)
     UInt(slice.foldRight(BigInt(0)) { case (x,y) => (y << 8) + (x.toInt & 0xFF) }, byteWidth*8)
@@ -52,7 +52,7 @@ class NastiROM(contents: Seq[Byte])(implicit p: Parameters) extends Module {
   io.b.valid := Bool(false)
 
   val byteWidth = io.r.bits.nastiXDataBits / 8
-  val rows = (contents.size + byteWidth - 1)/byteWidth + 1
+  val rows = (contents.size + byteWidth - 1)/byteWidth
   val rom = Vec.tabulate(rows) { i =>
     val slice = contents.slice(i*byteWidth, (i+1)*byteWidth)
     UInt(slice.foldRight(BigInt(0)) { case (x,y) => (y << 8) + (x.toInt & 0xFF) }, byteWidth*8)