diff --git a/.travis.yml b/.travis.yml
index ddbc3865..2589aabb 100644
--- a/.travis.yml
+++ b/.travis.yml
@@ -42,7 +42,7 @@ branches:
   except:
     - hwacha
     - boom
-    - hurricane
+    - /^hurricane.*$/
 
 before_install:
   - export CXX=g++-4.8 CC=gcc-4.8
diff --git a/firrtl b/firrtl
index 8b12dcbb..bcf73fb7 160000
--- a/firrtl
+++ b/firrtl
@@ -1 +1 @@
-Subproject commit 8b12dcbb76896a19f95dc4da19b3b8c74c1ddda3
+Subproject commit bcf73fb70969e5629a693c18f1f2ee7b37f14a76
diff --git a/src/main/scala/rocket/icache.scala b/src/main/scala/rocket/icache.scala
index 4f40228a..ef90453e 100644
--- a/src/main/scala/rocket/icache.scala
+++ b/src/main/scala/rocket/icache.scala
@@ -129,7 +129,7 @@ class ICache(latency: Int)(implicit p: Parameters) extends CoreModule()(p) with
       io.resp.bits.datablock := Mux1H(s1_tag_hit, s1_dout)
       io.resp.valid := s1_hit
     case 2 =>
-      val s2_hit = RegEnable(s1_hit, !stall)
+      val s2_hit = RegEnable(s1_hit, Bool(false), !stall)
       val s2_tag_hit = RegEnable(s1_tag_hit, !stall)
       val s2_dout = RegEnable(s1_dout, !stall)
       io.resp.bits.datablock := Mux1H(s2_tag_hit, s2_dout)
diff --git a/src/main/scala/uncore/axi4/Fragmenter.scala b/src/main/scala/uncore/axi4/Fragmenter.scala
index 05ca2b0d..939555cb 100644
--- a/src/main/scala/uncore/axi4/Fragmenter.scala
+++ b/src/main/scala/uncore/axi4/Fragmenter.scala
@@ -143,8 +143,8 @@ class AXI4Fragmenter(lite: Boolean = false, maxInFlight: Int = 32, combinational
     val writeSizes1 = slaves.map(s => s.supportsWrite.max/beatBytes-1)
 
     // Indirection variables for inputs and outputs; makes transformation application easier
-    val (in_ar, ar_last, _)       = fragment(in.ar, readSizes1)
-    val (in_aw, aw_last, w_beats) = fragment(in.aw, writeSizes1)
+    val (in_ar, ar_last, _)       = fragment(Queue.irrevocable(in.ar, 1, flow=true), readSizes1)
+    val (in_aw, aw_last, w_beats) = fragment(Queue.irrevocable(in.aw, 1, flow=true), writeSizes1)
     val in_w = in.w
     val in_r = in.r
     val in_b = in.b
diff --git a/vsim/Makefrag-verilog b/vsim/Makefrag-verilog
index 0f078a21..80df7160 100644
--- a/vsim/Makefrag-verilog
+++ b/vsim/Makefrag-verilog
@@ -14,7 +14,7 @@ $(generated_dir)/%.fir $(generated_dir)/%.prm $(generated_dir)/%.d: $(chisel_src
 
 $(generated_dir)/$(long_name).v $(generated_dir)/$(long_name).conf : $(firrtl) $(FIRRTL_JAR)
 	mkdir -p $(dir $@)
-	$(FIRRTL) -i $< -o $(generated_dir)/$(long_name).v -X verilog --inferRW $(MODEL) --replSeqMem -c:$(MODEL):-o:$(generated_dir)/$(long_name).conf
+	$(FIRRTL) -i $< -o $(generated_dir)/$(long_name).v -X verilog --infer-rw $(MODEL) --repl-seq-mem -c:$(MODEL):-o:$(generated_dir)/$(long_name).conf
 
 $(generated_dir)/$(long_name).behav_srams.v : $(generated_dir)/$(long_name).conf $(mem_gen)
 	cd $(generated_dir) && \