From 8c7e29eacd5a05dec569decf2a614e4f3bd458b2 Mon Sep 17 00:00:00 2001 From: Palmer Dabbelt Date: Sun, 6 Mar 2016 16:32:14 -0800 Subject: [PATCH] Avoid generating 0-width UInts Chisel3 requires a 1-bit width to represent UInt(0). --- uncore/src/main/scala/cache.scala | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/uncore/src/main/scala/cache.scala b/uncore/src/main/scala/cache.scala index d3c704c0..e555b003 100644 --- a/uncore/src/main/scala/cache.scala +++ b/uncore/src/main/scala/cache.scala @@ -1116,7 +1116,10 @@ class L2WritebackUnit(trackerId: Int)(implicit p: Parameters) extends L2XactTrac val xact_vol_irel_src = Reg{ io.irel().client_id } val xact_vol_irel_client_xact_id = Reg{ io.irel().client_xact_id } - val xact_addr_block = Cat(xact.tag, xact.idx, UInt(cacheId, cacheIdBits)) + val xact_addr_block = if (cacheIdBits == 0) + Cat(xact.tag, xact.idx) + else + Cat(xact.tag, xact.idx, UInt(cacheId, cacheIdBits)) val xact_vol_irel = Release( src = xact_vol_irel_src, voluntary = Bool(true),