From 8c459df3b601f3c6b81d5f5f199d640a68d1e4b1 Mon Sep 17 00:00:00 2001 From: Yunsup Lee Date: Fri, 28 Feb 2014 22:50:34 -0800 Subject: [PATCH] flush deck when xcpt occurs, fixes remaining p test bugs --- riscv-tools | 2 +- src/main/scala/RocketChip.scala | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/riscv-tools b/riscv-tools index 116e2f99..cc599fce 160000 --- a/riscv-tools +++ b/riscv-tools @@ -1 +1 @@ -Subproject commit 116e2f99b5d6b2174a89e69672049230a3bdc5f9 +Subproject commit cc599fce1ad7f0823c032f7c8dde0c0c363bad7d diff --git a/src/main/scala/RocketChip.scala b/src/main/scala/RocketChip.scala index 4cf98468..d258113b 100644 --- a/src/main/scala/RocketChip.scala +++ b/src/main/scala/RocketChip.scala @@ -258,7 +258,7 @@ class Top extends Module { val hc = hwacha.HwachaConfiguration(vic, dc, 8, 256, ndtlb = 8, nptlb = 2) val rc = RocketConfiguration(tl, ic, dc, fpu = HAS_FPU - //,rocc = (c: RocketConfiguration) => (new hwacha.Hwacha(hc, c)) + ,rocc = (c: RocketConfiguration) => (new hwacha.Hwacha(hc, c)) ) val io = new VLSITopIO(HTIF_WIDTH)